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Added test bench #7

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53 changes: 26 additions & 27 deletions Wallace5x5/final_adder.sv
Original file line number Diff line number Diff line change
@@ -1,33 +1,32 @@
// Design a 10-bit Carry Lookahead Adder
module final_adder(
input logic [9:0] a, // 10-bit input A
input logic [9:0] b, // 10-bit input B
output logic [9:0] s, // 10-bit sum output
output logic carry_out

module final_adder (
input logic [9:0] a,
input logic [9:0] b,
input logic c_in, // Carry input
output logic [9:0] sum,
output logic c_out // Carry output
);
logic [9:0] generate;
logic [9:0] propagate;
logic [10:0] carry;

// Generate and Propagate Logic
assign generate = a & b;
assign propagate = a | b;
logic [9:0] p, g, c;

//logic
assign carry[0] = 1'b0; //assumed to be 0
assign carry[1] = generate[0] | (propagate[0] & carry[0]);
assign carry[2] = generate[1] | (propagate[1] & carry[1]);
assign carry[3] = generate[2] | (propagate[2] & carry[2]);
assign carry[4] = generate[3] | (propagate[3] & carry[3]);
assign carry[5] = generate[4] | (propagate[4] & carry[4]);
assign carry[6] = generate[5] | (propagate[5] & carry[5]);
assign carry[7] = generate[6] | (propagate[6] & carry[6]);
assign carry[8] = generate[7] | (propagate[7] & carry[7]);
assign carry[9] = generate[8] | (propagate[8] & carry[8]);
assign carry_out = generate[9] | (propagate[9] & carry[9]);
// Generate propagate and generate
assign p = a ^ b; // Propagate
assign g = a & b; // Generate

// sum Calculation
assign s = a ^ b ^ carry[9:0];
// Carry lookahead
assign c[0] = c_in;
assign c[1] = g[0] | (p[0] & c[0]);
assign c[2] = g[1] | (p[1] & c[1]);
assign c[3] = g[2] | (p[2] & c[2]);
assign c[4] = g[3] | (p[3] & c[3]);
assign c[5] = g[4] | (p[4] & c[4]);
assign c[6] = g[5] | (p[5] & c[5]);
assign c[7] = g[6] | (p[6] & c[6]);
assign c[8] = g[7] | (p[7] & c[7]);
assign c[9] = g[8] | (p[8] & c[8]);
assign c_out = g[9] | (p[9] & c[9]); // Final carry out

endmodule
// Sum calculation
assign sum = p ^ c;

endmodule
43 changes: 43 additions & 0 deletions Wallace5x5/tb_final_adder.sv
Original file line number Diff line number Diff line change
@@ -0,0 +1,43 @@
module tb_final_adder;

logic [9:0] a, b;
logic c_in;
logic [9:0] sum;
logic c_out;

// Instantiate the 10-bit Carry Lookahead Adder
final_adder uut (
.a(a),
.b(b),
.c_in(c_in),
.sum(sum),
.c_out(c_out)
);

initial begin
// Test Case 1: 0 + 0
a = 10'b0000000000;
b = 10'b0000000000;
c_in = 1'b0;
#10;
$display("Test 1: a = %b, b = %b, sum = %b, carry out = %b", a, b, sum, c_out);

// Test Case 2: Random values
a = 10'b1010101010;
b = 10'b0101010101;
c_in = 1'b0;
#10;
$display("Test 2: a = %b, b = %b, sum = %b, carry out = %b", a, b, sum, c_out);

// Test Case 3: Overflow scenario
a = 10'b1111111111;
b = 10'b0000000001;
c_in = 1'b0;
#10;
$display("Test 3: a = %b, b = %b, sum = %b, carry out = %b", a, b, sum, c_out);

// Finish the simulation
$finish;
end

endmodule