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merged changes in axis
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@alexforencich
alexforencich committed Jun 1, 2021
2 parents b09e01b + 892ee84 commit 0512664
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636 changes: 374 additions & 262 deletions lib/axis/.test_durations
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80 changes: 40 additions & 40 deletions lib/axis/README.md
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Expand Up @@ -14,171 +14,171 @@ utilize [cocotbext-axi](https://github.com/alexforencich/cocotbext-axi).

## Documentation

### arbiter module
### `arbiter` module

General-purpose parametrizable arbiter. Supports priority and round-robin
arbitration. Supports blocking until request release or acknowledge.

### axis_adapter module
### `axis_adapter` module

The axis_adapter module bridges AXI stream busses of differing widths. The
The `axis_adapter` module bridges AXI stream buses of differing widths. The
module is parametrizable, but there are certain restrictions. First, the bus
word widths must be identical (e.g. one 8-bit lane and eight 8-bit lanes, but
not one 16-bit lane and one 32-bit lane). Second, the bus widths must be
related by an integer multiple (e.g. 2 words and 6 words, but not 4 words
and 6 words). Wait states will be inserted on the wider bus side when
necessary.

### axis_arb_mux module
### `axis_arb_mux` module

Frame-aware AXI stream arbitrated muliplexer with parametrizable data width
Frame-aware AXI stream arbitrated multiplexer with parametrizable data width
and port count. Supports priority and round-robin arbitration.

Wrappers can generated with axis_arb_mux_wrap.py.
Wrappers can generated with `axis_arb_mux_wrap.py`.

### axis_async_fifo module
### `axis_async_fifo` module

Configurable word-based or frame-based asynchronous FIFO with parametrizable
data width, depth, type, and bad frame detection. Supports power of two
depths only.

### axis_async_fifo_adapter module
### `axis_async_fifo_adapter` module

Configurable word-based or frame-based asynchronous FIFO with parametrizable
data width, depth, type, and bad frame detection. Supports different input
and output data widths, inserting an axis_adapter instance appropriately.
Supports power of two depths only.

### axis_broadcast module
### `axis_broadcast` module

AXI stream broadcaster. Duplicates one input stream across multiple output
streams.

### axis_cobs_decode
### `axis_cobs_decode`

Consistent Overhead Byte Stuffing (COBS) decoder. Fixed 8 bit width.

### axis_cobs_encode
### `axis_cobs_encode`

Consistent Overhead Byte Stuffing (COBS) encoder. Fixed 8 bit width.
Configurable zero insertion.

### axis_crosspoint module
### `axis_crosspoint` module

Basic crosspoint switch. tready signal not supported. Parametrizable data
Basic crosspoint switch. `tready` signal not supported. Parametrizable data
width.

Wrappers can generated with axis_crosspoint_wrap.py.
Wrappers can generated with `axis_crosspoint_wrap.py`.

### axis_demux module
### `axis_demux` module

Frame-aware AXI stream demuliplexer with parametrizable data width and port
Frame-aware AXI stream demultiplexer with parametrizable data width and port
count.

### axis_fifo module
### `axis_fifo` module

Configurable word-based or frame-based synchronous FIFO with parametrizable
data width, depth, type, and bad frame detection. Supports power of two
depths only.

### axis_fifo_adapter module
### `axis_fifo_adapter` module

Configurable word-based or frame-based synchronous FIFO with parametrizable
data width, depth, type, and bad frame detection. Supports different input
and output data widths, inserting an axis_adapter instance appropriately.
Supports power of two depths only.

### axis_frame_join module
### `axis_frame_join` module

Frame joiner with optional tag and parametrizable port count. 8 bit data path
only.

Wrappers can generated with axis_frame_join_wrap.py.
Wrappers can generated with `axis_frame_join_wrap.py`.

### axis_frame_length_adjust module
### `axis_frame_length_adjust` module

Frame length adjuster module. Truncates or pads frames as necessary to meet
the specified minimum and maximum length. Reports the original and current
lengths as well as whether the packet was truncated or padded. Length limits
are configurable at run time.

### axis_frame_length_adjust_fifo module
### `axis_frame_length_adjust_fifo` module

Frame length adjuster module with FIFO. Truncates or pads frames as necessary
to meet the specified minimum and maximum length. Reports the original and
current lengths as well as whether the packet was truncated or padded. FIFOs
are used so that the status information can be read before the packet itself.
Length limits are configurable at run time.

### axis_ll_bridge module
### `axis_ll_bridge` module

AXI stream to LocalLink bridge.

### axis_mux module
### `axis_mux` module

Frame-aware AXI stream muliplexer with parametrizable data width and port
Frame-aware AXI stream multiplexer with parametrizable data width and port
count.

Wrappers can generated with axis_mux_wrap.py.
Wrappers can generated with `axis_mux_wrap.py`.

### axis_pipeline_register module
### `axis_pipeline_register` module

Parametrizable register pipeline. LENGTH parameter determines number of
register stages.

### axis_ram_switch module
### `axis_ram_switch` module

Frame-aware AXI stream RAM switch with parametrizable data width, port count,
and FIFO size. Uses block RAM for storing packets in transit, time-sharing
the RAM interface between ports. Functionally equivalent to a combination of
per-port frame FIFOs and width converters connected to an AXI stream switch.

### axis_rate_limit module
### `axis_rate_limit` module

Fractional rate limiter, supports word and frame modes. Inserts wait states
to limit data rate to specified ratio. Frame mode inserts wait states at end
of frames, word mode ignores frames and inserts wait states at any point.
Parametrizable data width. Rate and mode are configurable at run time.

### axis_register module
### `axis_register` module

Datapath register with parameter to select between skid buffer, simple buffer,
and bypass. Use to improve timing for long routes.

### axis_srl_fifo module
### `axis_srl_fifo` module

SRL-based FIFO. Good for small FIFOs. SRLs on Xilinx FPGAs have a very fast
input setup time, so this module can be used to aid in timing closure.

### axis_srl_register module
### `axis_srl_register` module

SRL-based register. SRLs on Xilinx FPGAs have a very fast input setup time,
so this module can be used to aid in timing closure.

### axis_stat_counter module
### `axis_stat_counter` module

Statistics counter module. Counts bytes and frames passing through monitored
AXI stream interface. Trigger signal used to reset and dump counts out of AXI
interface, along with tag value. Use with axis_frame_join_N to form a single
interface, along with tag value. Use with `axis_frame_join` to form a single
monolithic frame from multiple monitored points with the same trigger.

### axis_switch module
### `axis_switch` module

Frame-aware AXI stream switch with parametrizable data width and port count.

Wrappers can generated with axis_switch_wrap.py.
Wrappers can generated with `axis_switch_wrap.py`.

### axis_tap module
### `axis_tap` module

AXI stream tap module. Used to make a copy of an AXI stream bus without
affecting the bus. Back-pressure on the output results in truncated frames
with tuser set.
with `tuser` set.

### ll_axis_bridge module
### `ll_axis_bridge` module

LocalLink to AXI stream bridge.

### priority_encoder module
### `priority_encoder` module

Parametrizable priority encoder.

Expand Down
36 changes: 29 additions & 7 deletions lib/axis/rtl/axis_ram_switch.v
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Expand Up @@ -184,8 +184,18 @@ initial begin

if (M_BASE == 0) begin
// M_BASE is zero, route with tdest as port index
$display("Addressing configuration for axis_switch instance %m");
for (i = 0; i < M_COUNT; i = i + 1) begin
$display("%d: %08x-%08x (connect mask %b)", i, i << (DEST_WIDTH-CL_M_COUNT), ((i+1) << (DEST_WIDTH-CL_M_COUNT))-1, M_CONNECT[i*S_COUNT +: S_COUNT]);
end

end else if (M_TOP == 0) begin
// M_TOP is zero, assume equal to M_BASE
$display("Addressing configuration for axis_switch instance %m");
for (i = 0; i < M_COUNT; i = i + 1) begin
$display("%d: %08x (connect mask %b)", i, M_BASE[i*DEST_WIDTH +: DEST_WIDTH], M_CONNECT[i*S_COUNT +: S_COUNT]);
end

for (i = 0; i < M_COUNT; i = i + 1) begin
for (j = i+1; j < M_COUNT; j = j + 1) begin
if (M_BASE[i*DEST_WIDTH +: DEST_WIDTH] == M_BASE[j*DEST_WIDTH +: DEST_WIDTH]) begin
Expand All @@ -197,6 +207,11 @@ initial begin
end
end
end else begin
$display("Addressing configuration for axis_switch instance %m");
for (i = 0; i < M_COUNT; i = i + 1) begin
$display("%d: %08x-%08x (connect mask %b)", i, M_BASE[i*DEST_WIDTH +: DEST_WIDTH], M_TOP[i*DEST_WIDTH +: DEST_WIDTH], M_CONNECT[i*S_COUNT +: S_COUNT]);
end

for (i = 0; i < M_COUNT; i = i + 1) begin
if (M_BASE[i*DEST_WIDTH +: DEST_WIDTH] > M_TOP[i*DEST_WIDTH +: DEST_WIDTH]) begin
$error("Error: invalid range (instance %m)");
Expand Down Expand Up @@ -413,16 +428,23 @@ generate
select_valid_next = select_valid_reg && !(port_axis_tvalid && port_axis_tready && port_axis_tlast);

if (port_axis_tvalid && !select_valid_reg && !drop_reg) begin
select_next = 1'b0;
select_next = 0;
select_valid_next = 1'b0;
drop_next = 1'b1;
for (k = 0; k < M_COUNT; k = k + 1) begin
if (M_BASE == 0) begin
// M_BASE is zero, route with $clog2(M_COUNT) MSBs of tdest as port index
if (port_axis_tdest[DEST_WIDTH-CL_M_COUNT +: CL_M_COUNT] == k && (M_CONNECT & (1 << (m+k*S_COUNT)))) begin
select_next = k;
if (M_COUNT == 1) begin
// M_BASE is zero with only one output port, ignore tdest
select_next = 0;
select_valid_next = 1'b1;
drop_next = 1'b0;
end else begin
// M_BASE is zero, route with $clog2(M_COUNT) MSBs of tdest as port index
if (port_axis_tdest[DEST_WIDTH-CL_M_COUNT +: CL_M_COUNT] == k && (M_CONNECT & (1 << (m+k*S_COUNT)))) begin
select_next = k;
select_valid_next = 1'b1;
drop_next = 1'b0;
end
end
end else if (M_TOP == 0) begin
// M_TOP is zero, assume equal to M_BASE
Expand Down Expand Up @@ -657,7 +679,7 @@ generate
cmd_table_start_addr_end = wr_ptr_cur_reg + 1;
cmd_table_start_len = len_reg;
cmd_table_start_select = select_reg;
cmd_table_start_tkeep = S_KEEP_ENABLE ? port_axis_tkeep : 1'b1;
cmd_table_start_tkeep = port_axis_tkeep;
cmd_table_start_tid = port_axis_tid;
cmd_table_start_tdest = port_axis_tdest;
cmd_table_start_tuser = port_axis_tuser;
Expand All @@ -669,7 +691,7 @@ generate

// read
cmd_valid_next = cmd_valid_reg & ~port_cmd_ready;
if (!cmd_valid_reg && cmd_table_active[cmd_table_read_ptr_reg[CMD_ADDR_WIDTH-1:0]] && cmd_table_read_ptr_reg != cmd_table_start_ptr_reg) begin
if (!cmd_valid_reg && cmd_table_active[cmd_table_read_ptr_reg[CMD_ADDR_WIDTH-1:0]] && cmd_table_read_ptr_reg != cmd_table_start_ptr_reg && (!ram_wr_en_reg || ram_wr_ack)) begin
cmd_table_read_en = 1'b1;
cmd_addr_next = cmd_table_addr_start[cmd_table_read_ptr_reg[CMD_ADDR_WIDTH-1:0]];
cmd_len_next = cmd_table_len[cmd_table_read_ptr_reg[CMD_ADDR_WIDTH-1:0]];
Expand Down Expand Up @@ -747,7 +769,7 @@ generate

if (cmd_table_finish_en) begin
cmd_table_finish_ptr_reg <= cmd_table_finish_ptr_reg + 1;
cmd_table_active[cmd_table_finish_ptr_reg[CMD_ADDR_WIDTH-1:0]] <= 1'b1;
cmd_table_active[cmd_table_finish_ptr_reg[CMD_ADDR_WIDTH-1:0]] <= 1'b0;
end

if (rst) begin
Expand Down
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