Rename Arista_7132LB to DCS7132LB

Signed-off-by: Alex Forencich <[email protected]>
alexforencich · Jan 14, 2024 · a05d1a4 · a05d1a4
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diff --git a/example/Arista_7132LB/fpga_25g/README.md → example/DCS7132LB/fpga_25g/README.md b/example/Arista_7132LB/fpga_25g/README.md → example/DCS7132LB/fpga_25g/README.md
diff --git a/...e/Arista_7132LB/fpga_25g/common/vivado.mk → example/DCS7132LB/fpga_25g/common/vivado.mk b/...e/Arista_7132LB/fpga_25g/common/vivado.mk → example/DCS7132LB/fpga_25g/common/vivado.mk
diff --git a/example/Arista_7132LB/fpga_25g/fpga.xdc → example/DCS7132LB/fpga_25g/fpga.xdc b/example/Arista_7132LB/fpga_25g/fpga.xdc → example/DCS7132LB/fpga_25g/fpga.xdc
diff --git a/example/Arista_7132LB/fpga_25g/fpga/Makefile → example/DCS7132LB/fpga_25g/fpga/Makefile b/example/Arista_7132LB/fpga_25g/fpga/Makefile → example/DCS7132LB/fpga_25g/fpga/Makefile
diff --git a/...le/Arista_7132LB/fpga_25g/fpga/config.tcl → example/DCS7132LB/fpga_25g/fpga/config.tcl b/...le/Arista_7132LB/fpga_25g/fpga/config.tcl → example/DCS7132LB/fpga_25g/fpga/config.tcl
diff --git a/.../Arista_7132LB/fpga_25g/fpga_10g/Makefile → example/DCS7132LB/fpga_25g/fpga_10g/Makefile b/.../Arista_7132LB/fpga_25g/fpga_10g/Makefile → example/DCS7132LB/fpga_25g/fpga_10g/Makefile
diff --git a/...rista_7132LB/fpga_25g/fpga_10g/config.tcl → ...le/DCS7132LB/fpga_25g/fpga_10g/config.tcl b/...rista_7132LB/fpga_25g/fpga_10g/config.tcl → ...le/DCS7132LB/fpga_25g/fpga_10g/config.tcl
diff --git a/...Arista_7132LB/fpga_25g/ip/eth_xcvr_gt.tcl → ...ple/DCS7132LB/fpga_25g/ip/eth_xcvr_gt.tcl b/...Arista_7132LB/fpga_25g/ip/eth_xcvr_gt.tcl → ...ple/DCS7132LB/fpga_25g/ip/eth_xcvr_gt.tcl
diff --git a/example/Arista_7132LB/fpga_25g/lib/eth → example/DCS7132LB/fpga_25g/lib/eth b/example/Arista_7132LB/fpga_25g/lib/eth → example/DCS7132LB/fpga_25g/lib/eth
diff --git a/.../fpga_25g/rtl/eth_xcvr_phy_quad_wrapper.v → .../fpga_25g/rtl/eth_xcvr_phy_quad_wrapper.v b/.../fpga_25g/rtl/eth_xcvr_phy_quad_wrapper.v → .../fpga_25g/rtl/eth_xcvr_phy_quad_wrapper.v
diff --git a/...132LB/fpga_25g/rtl/eth_xcvr_phy_wrapper.v → ...132LB/fpga_25g/rtl/eth_xcvr_phy_wrapper.v b/...132LB/fpga_25g/rtl/eth_xcvr_phy_wrapper.v → ...132LB/fpga_25g/rtl/eth_xcvr_phy_wrapper.v
diff --git a/example/Arista_7132LB/fpga_25g/rtl/fpga.v → example/DCS7132LB/fpga_25g/rtl/fpga.v b/example/Arista_7132LB/fpga_25g/rtl/fpga.v → example/DCS7132LB/fpga_25g/rtl/fpga.v
diff --git a/...le/Arista_7132LB/fpga_25g/rtl/fpga_core.v → example/DCS7132LB/fpga_25g/rtl/fpga_core.v b/...le/Arista_7132LB/fpga_25g/rtl/fpga_core.v → example/DCS7132LB/fpga_25g/rtl/fpga_core.v
diff --git a/.../Arista_7132LB/fpga_25g/rtl/sync_signal.v → example/DCS7132LB/fpga_25g/rtl/sync_signal.v b/.../Arista_7132LB/fpga_25g/rtl/sync_signal.v → example/DCS7132LB/fpga_25g/rtl/sync_signal.v
diff --git a/...sta_7132LB/fpga_25g/tb/fpga_core/Makefile → .../DCS7132LB/fpga_25g/tb/fpga_core/Makefile b/...sta_7132LB/fpga_25g/tb/fpga_core/Makefile → .../DCS7132LB/fpga_25g/tb/fpga_core/Makefile
diff --git a/...B/fpga_25g/tb/fpga_core/test_fpga_core.py → ...B/fpga_25g/tb/fpga_core/test_fpga_core.py b/...B/fpga_25g/tb/fpga_core/test_fpga_core.py → ...B/fpga_25g/tb/fpga_core/test_fpga_core.py
diff --git a/...LB/fpga_25g/tb/fpga_core/test_fpga_core.v → ...LB/fpga_25g/tb/fpga_core/test_fpga_core.v b/...LB/fpga_25g/tb/fpga_core/test_fpga_core.v → ...LB/fpga_25g/tb/fpga_core/test_fpga_core.v