Welcome to verilog-ethernet Discussions!

[alexforencich]

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[quyphamdev]

Hello,
I am looking for UDP/IP HDL core to add to my Quartus project with Triple-Speed Ethernet Intel FPGA IP. Does your UDP/IP work with Intel's IPs ?
Thanks.

[alexforencich]

Never tried it, but in principle there is no reason it shouldn't work. You will likely need to adapt Avalon-ST to AXI stream. Unfortunately, I do not currently have shims to do this.

[quyphamdev]

Thanks for a quick response.

[zyq-77]

Hello,
I use your example design on Xilinx KC705 and find that the design can't process fragmented network frame. Is there a problem with my usage? Where can I modify the code to achieve this function?
Thanks.

[alexforencich]

It doesn't support it because it's a gigantic pain. You have to store all of the received fragments somewhere and keep them organized until all of the other fragments come in and the frame can be assembled. And you have to handle cases where you're missing fragments and/or they don't arrive in order. And they are guaranteed to be interleaved with other traffic, so all of this has to be done as an offshoot, and then the results merged back in later on. And if block RAM isn't large enough, then you need to rope in DRAM, etc. etc. etc. If you want fragmentation support, use a software stack.

Incidentally, TCP is also not supported for a similar reason. You have to maintain a window of packets per connection on both TX and RX, handle retransmits and timeouts, handle multiple connections in parallel, etc. And you need to have some reasonable interface to the user design that can support multiple connections and separate backpressure on each connection, etc.

The current stack is basically just packet parsing and de-parsing along with some checksum computation. Very simple and straightforward compared to what you need to do to handle TCP connections, fragmentation, etc.

[Winters123]

just a random thought: Does it make sense to integrate corundum with a TCP/IP core (like this) so that corundum will be able to support TCP-based application offloading?

[alexforencich]

Well, you can put whatever you like between the DMA engine and the wire. That specific code will not be integrated as it's written in HLS and hence cannot be simulated with the current simulation framework (cocotb + icarus verilog). It's also not clear if code written for Xilinx HLS will be portable to, say, Intel devices, which are on the roadmap for corundum. The core of corundum is 100% pure verilog for the widest possible device and tool support, and that's not something I'm going to sacrifice any time soon. I'm also not sure if it makes much sense to actually offload TCP, vs a simpler segmentation offload such as LSO. I am considering implementing LSO as part of the variable-length descriptor support, which is much simpler in comparison to full TCP offload as the network stack still handles the actual protocol.

[Helix2551]

Hello,
I am quite new in the FPGA world and will use https://github.com/corundum/corundum concept with my NetFPGA sume board.
I wanna use a SFP port for CAN bus, so the PHY Modul should meet the needed requirements.
Corundum linked this Git repository regarding their PHY Moduls.
Would you please so kind, and help me how I can figure out if the PHY Modul can use CAN ?
Thanks a lot

[alexforencich]

CAN bus? I don't think you can use the transceivers for CAN. It's not compatible electrically. You'll want to use the PMODs for CAN, and use an external CAN transceiver chip.

[Helix2551]

Ok thank you for this advise :)

[ntut317]

Hello, I am currently studying at Taipei University of Technology and the grade is the master's degree.Now I am developing chips for transmission protocol conversion. Sincerely hope you can give me some suggest about the transfer protocol conversion. If you have time, please contact me. My E-mail is [email protected], Thank you.

[QuestionAccount101]

Hello Alex, your coding is amazing! I have been working with your code and I am having issues with AXIS_ADAPTER. I can expand an AXIS going from 1byte to 2 bytes but going back down to 1 byte creates an issue. The code seems to manage the first byte correctly and drops the remaining. Any advice?

[alexforencich]

I will need to see either the code or a waveform to be able to figure out what the issue is, my assumption is something is either not properly connected or not properly configured.

[QuestionAccount101]

Hello. I just grabbed the AXIS output from your eth_mac_1g_fifo instantiation and created 2 instances of axis_adapter in the RX path. The first with S_DATA_WIDTH = 8 and M_DATA_WIDTH = 16, the second with S_DATA_WIDTH = 16 and M_DATA_WIDTH = 8. Then pass that output to your eth_axis_rx and so on for the loop. Using Wireshark I discovered only every other byte was getting returned. I will play with your code and see what I come up with and will get in touch again after I have figured it out. Thank you again, you are an epic Verilog coder.

[alexforencich]

Sounds like you might have the width wrong on the data signal, and the upper 8 bits are getting cut off.

[hemanthr28]

Hello, I am master's student in Computer Engineering. Currently working on a DSM problem. I am using Bittware 250 SoC for my work.
I am now working on porting the design to my FPGA. I referred the porting guide, as a first step, I need to create example design for verilog-ethernet and pcie. Can anyone please guide me on how to get started to create the example designs, I am completely new to FPGA developement.
My question is, do I use the pcie IP block in Vivado or do I need to modify some existing examples? If someone can brief me on how the flow is, it will be of great help. Thank you.

[alexforencich]

Are you referring to the Corundum porting guide? Anyway, creating new example designs generally just means making a copy of an existing one and editing it to run on your device. The 250 SoC has a Zynq MPSOC part on it, so presumably it will be quite similar to the ZCU106 design, except with GTY instead of GTH transceivers. TBH, if you're porting Corundum, then you can probably just make a copy of one of the Corundum designs and go from there; porting the PCIe and Ethernet designs separately is mainly important for porting to a new FPGA family, as opposed to a new board that uses an FPGA family that's already supported.

[hemanthr28]

Thank you for the information.

[astirabaloch]

Hello, I hope you are doing great.
I am using your verilog-ethernet module to send the UDP packets from DE2-115 to PC. Example design "Echo" is working fine. Now I have edited for transmission only. Setup is like that I've a fifo which feed the packets to "udp_payload_fifo". Here I have assumed that only sending the data to this fifo will be sufficient for transmission. This fifo gets full and do not transmit to module "udp_complete" . Every other signal is exactly like in Echo example. Is there anything else that I need to control for transmission ?
I have commented "rx_udp_hdr_ready" and "tx_udp_hdr_ready" is set to 1. Module "eth_axis_rx" is also commented.
Any help would be appreciated. Thanks.

[ziyangzhang0403]

hello, I use another board but have the same question with you. I can not just transmission data from FPGA to PC.
have you solved this problem?
thank u

[v-ashwin]

Can you please share the ethernet specification, which you had referred? We need that to understand the design and test scenarios.

[alexforencich]

Ethernet spec: https://ieeexplore.ieee.org/document/9844436 . You should be able to download it for free via the IEEE GET program (https://ieeexplore.ieee.org/browse/standards/get-program/page), basically just create an IEEE login and you should be able to download it. For UDP, etc. I was mainly looking at Wikipedia and RFCs.

[v-ashwin]

Alex,
Thanks for your reply. Now we are referring to the IEEE spec and trying to add registers to the design. We are currently working with interrupts. Have you implemented interrupts in your implementation? I was trying to search for IRQ_TXE / IRQ_RXE and other required registers but could not find in the RTL, are we missing something.

[dinakaran2805]

Hello @alexforencich,

I'm going through your work and I'm very impressed with it. I'm currently working on writing a top module in Verilog with instances of MII, GMII, and RGMII modules. I would greatly appreciate it if I could gain more clarity regarding the clock and reset used in the design.

From my understanding of your code, I have identified that in GMII and RGMII, "gtx_clk" operates at 125MHZ (with a time period of 8ns) to achieve a speed of 1Gbps. Additionally, there is a clock named "logic_clk," which I assume can run at any frequency (preferably greater than 125MHZ). However, in the MII module, the "logic_clk" runs at 25MHZ for 100Mbps.

In my top module, I am planning to include a global clock "CLK," which operates at either 1GHZ or 2GHZ.

I have a few queries:

1. Could you explain the purpose of "logic_clk" in MII and GMII/GMII? Is it feasible to use the same "logic_clk" for both MII and GMII/RGMII?
2. Is it possible for me to replace the "logic_clk" with my global clock "CLK"?
3. I noticed that the MII module has a reset "rst" in addition to "logic_rst." Could you clarify the purpose of the "rst"?

Any assistance on these questions would be greatly appreciated. Thank you.