A 4-stage pipelined RISC-V core
- FyraVortex = Fyra + Vortex
- Fyra = Four in Swedish
- Vortex = Speedy and Dynamic
- Primitives - Register, AND, OR, MUXs
- Decoder
- Sign Extender
- Control Unit
- ALU
- Register File
- Memory Controller
- Data Memory
- Instruction Memory
- Forwarding Unit
- Hazard Detection Unit
- Instruction Fetch
- Instruction Decode
- Instruction Execute
- Data Write Back