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csr.{reg,action}: update tests to follow RFC #27.
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jfng committed Feb 9, 2024
1 parent 571079a commit 1e1490e
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Showing 2 changed files with 30 additions and 44 deletions.
29 changes: 12 additions & 17 deletions tests/test_csr_action.py
Original file line number Diff line number Diff line change
Expand Up @@ -20,12 +20,12 @@ def test_sim(self):
def process():
yield dut.r_data.eq(0xa)
yield dut.port.r_stb.eq(1)
yield Settle()
yield Delay()
self.assertEqual((yield dut.port.r_data), 0xa)
self.assertEqual((yield dut.r_stb), 1)

sim = Simulator(dut)
sim.add_process(process)
sim.add_testbench(process)
with sim.write_vcd(vcd_file=open("test.vcd", "w")):
sim.run()

Expand All @@ -43,12 +43,12 @@ def test_sim(self):
def process():
yield dut.port.w_data.eq(0xa)
yield dut.port.w_stb.eq(1)
yield Settle()
yield Delay()
self.assertEqual((yield dut.w_data), 0xa)
self.assertEqual((yield dut.w_stb), 1)

sim = Simulator(dut)
sim.add_process(process)
sim.add_testbench(process)
with sim.write_vcd(vcd_file=open("test.vcd", "w")):
sim.run()

Expand All @@ -75,14 +75,13 @@ def process():
self.assertEqual((yield dut.data), 0x5)
yield dut.port.w_stb .eq(1)
yield dut.port.w_data.eq(0xa)
yield
yield Settle()
yield Tick()
self.assertEqual((yield dut.port.r_data), 0xa)
self.assertEqual((yield dut.data), 0xa)

sim = Simulator(dut)
sim.add_clock(1e-6)
sim.add_sync_process(process)
sim.add_testbench(process)
with sim.write_vcd(vcd_file=open("test.vcd", "w")):
sim.run()

Expand Down Expand Up @@ -111,21 +110,19 @@ def process():
self.assertEqual((yield dut.data), 0xf)
yield dut.port.w_stb .eq(1)
yield dut.port.w_data.eq(0x5)
yield
yield Settle()
yield Tick()
self.assertEqual((yield dut.port.r_data), 0xa)
self.assertEqual((yield dut.data), 0xa)

yield dut.port.w_data.eq(0x3)
yield dut.set.eq(0x4)
yield
yield Settle()
yield Tick()
self.assertEqual((yield dut.port.r_data), 0xc)
self.assertEqual((yield dut.data), 0xc)

sim = Simulator(dut)
sim.add_clock(1e-6)
sim.add_sync_process(process)
sim.add_testbench(process)
with sim.write_vcd(vcd_file=open("test.vcd", "w")):
sim.run()

Expand Down Expand Up @@ -154,21 +151,19 @@ def process():
self.assertEqual((yield dut.data), 0x5)
yield dut.port.w_stb .eq(1)
yield dut.port.w_data.eq(0xa)
yield
yield Settle()
yield Tick()
self.assertEqual((yield dut.port.r_data), 0xf)
self.assertEqual((yield dut.data), 0xf)

yield dut.port.w_data.eq(0x3)
yield dut.clear.eq(0x7)
yield
yield Settle()
yield Tick()
self.assertEqual((yield dut.port.r_data), 0xb)
self.assertEqual((yield dut.data), 0xb)

sim = Simulator(dut)
sim.add_clock(1e-6)
sim.add_sync_process(process)
sim.add_testbench(process)
with sim.write_vcd(vcd_file=open("test.vcd", "w")):
sim.run()

Expand Down
45 changes: 18 additions & 27 deletions tests/test_csr_reg.py
Original file line number Diff line number Diff line change
@@ -1,7 +1,7 @@
import unittest
import warnings
from amaranth import *
from amaranth.hdl.ir import UnusedElaboratable
from amaranth.hdl import UnusedElaboratable
from amaranth.lib import wiring
from amaranth.lib.wiring import In, Out
from amaranth.sim import *
Expand Down Expand Up @@ -539,7 +539,7 @@ def process():
Const(0b00, 2), # e
Const(0b110, 3), # f
))
yield Settle()
yield Delay()

self.assertEqual((yield dut.f.a .port.w_stb), 0)
self.assertEqual((yield dut.f.b .port.w_stb), 1)
Expand All @@ -557,9 +557,9 @@ def process():
self.assertEqual((yield dut.f.e[0].w_data), 0b0)
self.assertEqual((yield dut.f.e[1].w_data), 0b0)

yield
yield Tick()
yield dut.element.w_stb.eq(0)
yield Settle()
yield Delay()

self.assertEqual((yield dut.f.b .data), 0b101)
self.assertEqual((yield dut.f.c.d.data), 0b00)
Expand All @@ -570,7 +570,7 @@ def process():
yield dut.f.a.r_data.eq(0b1)
yield dut.f.b.set .eq(0b010)
yield dut.f.f.clear .eq(0b010)
yield Settle()
yield Delay()

self.assertEqual((yield dut.element.r_data),
Const.cast(Cat(
Expand All @@ -581,11 +581,11 @@ def process():
Const(0b110, 3), # f
)).value)

yield
yield Tick()
yield dut.f.a.r_data.eq(0b0)
yield dut.f.b.set .eq(0b000)
yield dut.f.f.clear .eq(0b000)
yield Settle()
yield Delay()

self.assertEqual((yield dut.element.r_data),
Const.cast(Cat(
Expand All @@ -609,8 +609,7 @@ def process():

yield dut.f.b.set .eq(0b001)
yield dut.f.f.clear.eq(0b111)
yield
yield Settle()
yield Tick()

self.assertEqual((yield dut.element.r_data),
Const.cast(Cat(
Expand All @@ -626,7 +625,7 @@ def process():

sim = Simulator(dut)
sim.add_clock(1e-6)
sim.add_sync_process(process)
sim.add_testbench(process)
with sim.write_vcd(vcd_file=open("test.vcd", "w")):
sim.run()

Expand Down Expand Up @@ -930,8 +929,7 @@ def process():
yield dut.bus.r_stb.eq(1)
yield dut.bus.w_stb.eq(1)
yield dut.bus.w_data.eq(0xa)
yield
yield Settle()
yield Tick()
self.assertEqual((yield dut.bus.r_data), 0x0)
self.assertEqual((yield reg_rw_4 .f.a.port.r_stb), 1)
self.assertEqual((yield reg_rw_8 .f.a.port.r_stb), 0)
Expand All @@ -941,16 +939,14 @@ def process():
self.assertEqual((yield reg_rw_16.f.a.port.w_stb), 0)
yield dut.bus.r_stb.eq(0)
yield dut.bus.w_stb.eq(0)
yield
yield Settle()
yield Tick()
self.assertEqual((yield reg_rw_4.f.a.data), 0xa)

yield dut.bus.addr.eq(1)
yield dut.bus.r_stb.eq(1)
yield dut.bus.w_stb.eq(1)
yield dut.bus.w_data.eq(0xbb)
yield
yield Settle()
yield Tick()
self.assertEqual((yield dut.bus.r_data), 0x11)
self.assertEqual((yield reg_rw_4 .f.a.port.r_stb), 0)
self.assertEqual((yield reg_rw_8 .f.a.port.r_stb), 1)
Expand All @@ -960,16 +956,14 @@ def process():
self.assertEqual((yield reg_rw_16.f.a.port.w_stb), 0)
yield dut.bus.r_stb.eq(0)
yield dut.bus.w_stb.eq(0)
yield
yield Settle()
yield Tick()
self.assertEqual((yield reg_rw_8.f.a.data), 0xbb)

yield dut.bus.addr.eq(2)
yield dut.bus.r_stb.eq(1)
yield dut.bus.w_stb.eq(1)
yield dut.bus.w_data.eq(0xcc)
yield
yield Settle()
yield Tick()
self.assertEqual((yield dut.bus.r_data), 0x22)
self.assertEqual((yield reg_rw_4 .f.a.port.r_stb), 0)
self.assertEqual((yield reg_rw_8 .f.a.port.r_stb), 0)
Expand All @@ -979,16 +973,14 @@ def process():
self.assertEqual((yield reg_rw_16.f.a.port.w_stb), 0)
yield dut.bus.r_stb.eq(0)
yield dut.bus.w_stb.eq(0)
yield
yield Settle()
yield Tick()
self.assertEqual((yield reg_rw_16.f.a.data), 0x3322)

yield dut.bus.addr.eq(3)
yield dut.bus.r_stb.eq(1)
yield dut.bus.w_stb.eq(1)
yield dut.bus.w_data.eq(0xdd)
yield
yield Settle()
yield Tick()
self.assertEqual((yield dut.bus.r_data), 0x33)
self.assertEqual((yield reg_rw_4 .f.a.port.r_stb), 0)
self.assertEqual((yield reg_rw_8 .f.a.port.r_stb), 0)
Expand All @@ -998,12 +990,11 @@ def process():
self.assertEqual((yield reg_rw_16.f.a.port.w_stb), 1)
yield dut.bus.r_stb.eq(0)
yield dut.bus.w_stb.eq(0)
yield
yield Settle()
yield Tick()
self.assertEqual((yield reg_rw_16.f.a.data), 0xddcc)

sim = Simulator(dut)
sim.add_clock(1e-6)
sim.add_sync_process(process)
sim.add_testbench(process)
with sim.write_vcd(vcd_file=open("test.vcd", "w")):
sim.run()

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