csr.reg: add support for reserved fields.

amaranth-lang · Jan 12, 2024 · 24e7ee7 · 24e7ee7
1 parent 4923bb4
commit 24e7ee7
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Showing 4 changed files with 113 additions and 4 deletions.
diff --git a/amaranth_soc/csr/action.py b/amaranth_soc/csr/action.py
@@ -5,7 +5,7 @@
 from .reg import FieldPort
 
 
-__all__ = ["R", "W", "RW", "RW1C", "RW1S"]
+__all__ = ["R", "W", "RW", "RW1C", "RW1S", "ResRAW0", "ResRAWL", "ResR0WA", "ResR0W0"]
 
 
 class R(wiring.Component):
@@ -216,3 +216,48 @@ def elaborate(self, platform):
         ]
 
         return m
+
+
+class _Reserved(wiring.Component):
+    _doc_template = """
+    {description}
+
+    Parameters
+    ----------
+    shape : :ref:`shape-castable <lang-shapecasting>`
+        Shape of the field.
+
+    Interface attributes
+    --------------------
+    port : :class:`FieldPort`
+        Field port.
+    """
+    def __init__(self, shape):
+        super().__init__({"port": In(FieldPort.Signature(shape, access="nc"))})
+
+    def elaborate(self, platform):
+        return Module()
+
+
+class ResRAW0(_Reserved):
+    __doc__ = _Reserved._doc_template.format(description="""
+    A reserved read-any/write-zero field action.
+    """)
+
+
+class ResRAWL(_Reserved):
+    __doc__ = _Reserved._doc_template.format(description="""
+    A reserved read-any/write-last field action.
+    """)
+
+
+class ResR0WA(_Reserved):
+    __doc__ = _Reserved._doc_template.format(description="""
+    A reserved read-zero/write-any field action.
+    """)
+
+
+class ResR0W0(_Reserved):
+    __doc__ = _Reserved._doc_template.format(description="""
+    A reserved read-zero/write-zero field action.
+    """)
diff --git a/amaranth_soc/csr/reg.py b/amaranth_soc/csr/reg.py
@@ -16,6 +16,7 @@ class Access(enum.Enum):
         R  = "r"
         W  = "w"
         RW = "rw"
+        NC = "nc"
 
         def readable(self):
             return self == self.R or self == self.RW

diff --git a/tests/test_csr_action.py b/tests/test_csr_action.py
@@ -11,6 +11,8 @@ class RTestCase(unittest.TestCase):
     def test_simple(self):
         f = action.R(unsigned(4))
         self.assertEqual(f.r_data.shape(), unsigned(4))
+        self.assertTrue(f.port.access.readable())
+        self.assertFalse(f.port.access.writable())
 
     def test_sim(self):
         dut = action.R(unsigned(4))
@@ -30,6 +32,8 @@ class WTestCase(unittest.TestCase):
     def test_simple(self):
         f = action.W(unsigned(4))
         self.assertEqual(f.w_data.shape(), unsigned(4))
+        self.assertFalse(f.port.access.readable())
+        self.assertTrue(f.port.access.writable())
 
     def test_sim(self):
         dut = action.W(unsigned(4))
@@ -48,11 +52,16 @@ def process():
 class RWTestCase(unittest.TestCase):
     def test_simple(self):
         f4 = action.RW(unsigned(4), reset=0x5)
-        f8 = action.RW(signed(8))
         self.assertEqual(f4.data.shape(), unsigned(4))
         self.assertEqual(f4.reset, 0x5)
+        self.assertTrue(f4.port.access.readable())
+        self.assertTrue(f4.port.access.writable())
+
+        f8 = action.RW(signed(8))
         self.assertEqual(f8.data.shape(), signed(8))
         self.assertEqual(f8.reset, 0)
+        self.assertTrue(f8.port.access.readable())
+        self.assertTrue(f8.port.access.writable())
 
     def test_sim(self):
         dut = action.RW(unsigned(4), reset=0x5)
@@ -77,13 +86,18 @@ def process():
 class RW1CTestCase(unittest.TestCase):
     def test_simple(self):
         f4 = action.RW1C(unsigned(4), reset=0x5)
-        f8 = action.RW1C(signed(8))
         self.assertEqual(f4.data.shape(), unsigned(4))
         self.assertEqual(f4.set .shape(), unsigned(4))
         self.assertEqual(f4.reset, 0x5)
+        self.assertTrue(f4.port.access.readable())
+        self.assertTrue(f4.port.access.writable())
+
+        f8 = action.RW1C(signed(8))
         self.assertEqual(f8.data.shape(), signed(8))
         self.assertEqual(f8.set .shape(), signed(8))
         self.assertEqual(f8.reset, 0)
+        self.assertTrue(f8.port.access.readable())
+        self.assertTrue(f8.port.access.writable())
 
     def test_sim(self):
         dut = action.RW1C(unsigned(4), reset=0xf)
@@ -115,13 +129,18 @@ def process():
 class RW1STestCase(unittest.TestCase):
     def test_simple(self):
         f4 = action.RW1S(unsigned(4), reset=0x5)
-        f8 = action.RW1S(signed(8))
         self.assertEqual(f4.data .shape(), unsigned(4))
         self.assertEqual(f4.clear.shape(), unsigned(4))
         self.assertEqual(f4.reset, 0x5)
+        self.assertTrue(f4.port.access.readable())
+        self.assertTrue(f4.port.access.writable())
+
+        f8 = action.RW1S(signed(8))
         self.assertEqual(f8.data .shape(), signed(8))
         self.assertEqual(f8.clear.shape(), signed(8))
         self.assertEqual(f8.reset, 0)
+        self.assertTrue(f8.port.access.readable())
+        self.assertTrue(f8.port.access.writable())
 
     def test_sim(self):
         dut = action.RW1S(unsigned(4), reset=0x5)
@@ -148,3 +167,36 @@ def process():
         sim.add_sync_process(process)
         with sim.write_vcd(vcd_file=open("test.vcd", "w")):
             sim.run()
+
+
+class ResRAW0TestCase(unittest.TestCase):
+    def test_simple(self):
+        f = action.ResRAW0(unsigned(4))
+        self.assertEqual(f.port.shape, unsigned(4))
+        self.assertFalse(f.port.access.readable())
+        self.assertFalse(f.port.access.writable())
+        self.assertIsInstance(f.elaborate(platform=None), Module)
+
+class ResRAWLTestCase(unittest.TestCase):
+    def test_simple(self):
+        f = action.ResRAWL(unsigned(4))
+        self.assertEqual(f.port.shape, unsigned(4))
+        self.assertFalse(f.port.access.readable())
+        self.assertFalse(f.port.access.writable())
+        self.assertIsInstance(f.elaborate(platform=None), Module)
+
+class ResR0WATestCase(unittest.TestCase):
+    def test_simple(self):
+        f = action.ResR0WA(unsigned(4))
+        self.assertEqual(f.port.shape, unsigned(4))
+        self.assertFalse(f.port.access.readable())
+        self.assertFalse(f.port.access.writable())
+        self.assertIsInstance(f.elaborate(platform=None), Module)
+
+class ResR0W0TestCase(unittest.TestCase):
+    def test_simple(self):
+        f = action.ResR0W0(unsigned(4))
+        self.assertEqual(f.port.shape, unsigned(4))
+        self.assertFalse(f.port.access.readable())
+        self.assertFalse(f.port.access.writable())
+        self.assertIsInstance(f.elaborate(platform=None), Module)
diff --git a/tests/test_csr_reg.py b/tests/test_csr_reg.py
@@ -69,6 +69,17 @@ def test_shape_0_rw(self):
             "w_stb":  Out(1),
         }).members)
 
+    def test_shape_8_nc(self):
+        sig = FieldPort.Signature(8, "nc")
+        self.assertEqual(sig.shape, unsigned(8))
+        self.assertEqual(sig.access, FieldPort.Access.NC)
+        self.assertEqual(sig.members, wiring.Signature({
+            "r_data": In(unsigned(8)),
+            "r_stb":  Out(1),
+            "w_data": Out(unsigned(8)),
+            "w_stb":  Out(1),
+        }).members)
+
     def test_create(self):
         sig  = FieldPort.Signature(unsigned(8), "rw")
         port = sig.create(path=("foo", "bar"))