Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom

wishbone.bus: add Arbiter. #9

Merged
merged 1 commit into from
Feb 12, 2020
Merged

wishbone.bus: add Arbiter. #9

merged 1 commit into from
Feb 12, 2020

Conversation

jfng
Copy link
Member

@jfng jfng commented Feb 10, 2020

Wednesday Jan 22, 2020 at 14:18 GMT
Originally opened as m-labs/nmigen-soc#3

This arbiter should be compatible with all the optional features of wishbone.Interface.

The round-robin implementation could perhaps be moved to nmigen.lib and imported back here, but that would make nmigen-soc depend on a later revision than nmigen v0.1.

@jfng jfng mentioned this pull request Feb 10, 2020
Closed
@codecov
Copy link

codecov bot commented Feb 10, 2020 •
edited
Loading

Codecov Report

Merging #9 into master will increase coverage by 0.04%.
The diff coverage is 100%.

Impacted file tree graph

@@            Coverage Diff             @@
##           master       #9      +/-   ##
==========================================
+ Coverage   99.59%   99.63%   +0.04%     
==========================================
  Files           4        4              
  Lines         493      552      +59     
  Branches      107      127      +20     
==========================================
+ Hits          491      550      +59     
  Misses          1        1              
  Partials        1        1
Impacted Files Coverage Δ
nmigen_soc/wishbone/bus.py 98.97% <100%> (+0.44%) ⬆️

Continue to review full report at Codecov.

Legend - Click here to learn more
Δ = absolute <relative> (impact), ø = not affected, ? = missing data
Powered by Codecov. Last update f8f8982...87ab698. Read the comment docs.

whitequark
whitequark requested changes Feb 12, 2020
View reviewed changes
Copy link
Member

@whitequark whitequark left a comment

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Logic looks good to me overall, with one minor change I request.

I didn't try and exhaustively check every possible state; we should make sure that happens, but by adding more formal checks rather than manual work. For now that's fine though.

nmigen_soc/wishbone/bus.py Outdated
def __init__(self, *, addr_width, data_width, granularity=None, features=frozenset()):
self.bus = Interface(addr_width=addr_width, data_width=data_width,
granularity=granularity, features=features)
self._itors = []
Copy link
Member

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Nit: I seem to read itor as a shortening of iterator each time, when in context of Python. Could you use something else, e.g. intr?

Copy link
Member Author

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

intr makes me think of "interrupt", but it should be unambigous in the context of a Wishbone arbiter. Let's go with that.

Copy link
Member

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Me too, but I couldn't come up with anything better. It's just a private member anyway.

@jfng jfng merged commit 967a65f into amaranth-lang:master Feb 12, 2020
@jfng
Copy link
Member Author

jfng commented Feb 12, 2020

Thanks for the review !

Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Reviewers

@whitequark whitequark whitequark requested changes

Assignees
No one assigned
Labels
None yet
Milestone
No milestone
Development

Successfully merging this pull request may close these issues.
2 participants
@jfng @whitequark