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hdl.ir: bring new naming rules to top-level ports
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tpwrules committed Mar 23, 2024
1 parent f27560f commit a1fbbb2
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1 change: 1 addition & 0 deletions amaranth/hdl/_ir.py
Original file line number Diff line number Diff line change
Expand Up @@ -557,6 +557,7 @@ def _assign_port_names(self):
if name is None:
name = _add_name(assigned_names, conn.name)
assigned_names.add(name)
validate_name(name, "Top-level port name")
new_ports.append((name, conn, dir))
self.ports = new_ports

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6 changes: 6 additions & 0 deletions tests/test_hdl_ir.py
Original file line number Diff line number Diff line change
Expand Up @@ -1044,6 +1044,12 @@ def test_assign_names_to_fragments_duplicate(self):
self.assertEqual(design.fragments[a1_f].name, ("top", "a"))
self.assertEqual(design.fragments[a2_f].name, ("top", "a$1"))

def test_port_wrong_name(self):
f = Fragment()
with self.assertRaisesRegex(NameError,
r"^Top-level port name must be a non-empty string$"):
design = Design(f, ports=[("", Signal(), None)], hierarchy=("top",))


class ElaboratesTo(Elaboratable):
def __init__(self, lower):
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