Fix

amaranth-lang · May 10, 2024 · b1c8e83 · b1c8e83
1 parent b18f228
commit b1c8e83
Showing 1 changed file with 2 additions and 0 deletions.
diff --git a/amaranth/sim/pysim.py b/amaranth/sim/pysim.py
@@ -297,6 +297,8 @@ def traverse_traces(traces):
                         for trace_signal in trace._rhs_signals():
                             for name in self.gtkw_signal_names[trace_signal]:
                                 self.gtkw_save.trace(name)
+                elif isinstance(traces, ValueLike):
+                    traverse_traces(Value.cast(traces))
                 elif isinstance(traces, MemoryData):
                     for row_names in self.gtkw_memory_names[traces]:
                         for name in row_names: