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back.verilog: forbid Yosys version range with dangling else bug. #1051

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merged 1 commit into from
Jan 24, 2024

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Fixes #1049.

This can be merged once YosysHQ/yosys#4150 is in and the version range is final.

@whitequark whitequark added this to the 0.5 milestone Jan 23, 2024
@whitequark whitequark force-pushed the forbid-yosys-0.37 branch 4 times, most recently from 8a40d69 to f4a582b Compare January 23, 2024 04:13
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codecov bot commented Jan 23, 2024

Codecov Report

Attention: 1 lines in your changes are missing coverage. Please review.

Comparison is base (0ea2aa6) 86.52% compared to head (4b6e989) 86.48%.

Files Patch % Lines
amaranth/back/verilog.py 0.00% 1 Missing ⚠️
Additional details and impacted files
@@            Coverage Diff             @@
##             main    #1051      +/-   ##
==========================================
- Coverage   86.52%   86.48%   -0.05%     
==========================================
  Files          41       41              
  Lines        7153     7153              
  Branches     1709     1709              
==========================================
- Hits         6189     6186       -3     
- Misses        797      799       +2     
- Partials      167      168       +1     

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@whitequark whitequark marked this pull request as ready for review January 24, 2024 16:34
@whitequark whitequark enabled auto-merge January 24, 2024 16:35
@whitequark whitequark added this pull request to the merge queue Jan 24, 2024
@whitequark whitequark removed this pull request from the merge queue due to a manual request Jan 24, 2024
@whitequark whitequark enabled auto-merge January 24, 2024 16:39
@whitequark whitequark added this pull request to the merge queue Jan 24, 2024
Merged via the queue into amaranth-lang:main with commit 65d77f0 Jan 24, 2024
13 of 14 checks passed
@whitequark whitequark deleted the forbid-yosys-0.37 branch January 24, 2024 16:50
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Miscompilation of nested ifs
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