Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Move PySim name extraction functionality to Fragment and improve it #965

Merged
merged 2 commits into from
Nov 25, 2023

Conversation

whitequark
Copy link
Member

At the moment there are two issues with assignment of names in pysim:

  1. Names are not deduplicated. It is possible (and frequent) for names to be included twice in VCD output.
  2. Names are different compared to what is emitted in RTLIL, Verilog, or CXXRTL output.

This PR fixes issue (1), and issue (2) will be fixed by the new IR.

@whitequark whitequark added this to the 0.4 milestone Nov 25, 2023
Copy link

codecov bot commented Nov 25, 2023

Codecov Report

Attention: 2 lines in your changes are missing coverage. Please review.

Comparison is base (89d1c9b) 83.68% compared to head (153bc0c) 83.67%.

Files Patch % Lines
amaranth/hdl/ir.py 97.29% 0 Missing and 1 partial ⚠️
amaranth/sim/pysim.py 85.71% 1 Missing ⚠️
Additional details and impacted files
@@            Coverage Diff             @@
##             main     #965      +/-   ##
==========================================
- Coverage   83.68%   83.67%   -0.02%     
==========================================
  Files          54       54              
  Lines        7766     7784      +18     
  Branches     1905     1912       +7     
==========================================
+ Hits         6499     6513      +14     
- Misses       1058     1062       +4     
  Partials      209      209              

☔ View full report in Codecov by Sentry.
📢 Have feedback on the report? Share it here.

At the moment there are two issues with assignment of names in pysim:
1. Names are not deduplicated. It is possible (and frequent) for names
   to be included twice in VCD output.
2. Names are different compared to what is emitted in RTLIL, Verilog,
   or CXXRTL output.

This commit fixes issue (1), and issue (2) will be fixed by the new IR.
@whitequark whitequark added this pull request to the merge queue Nov 25, 2023
Merged via the queue into amaranth-lang:main with commit 79adbed Nov 25, 2023
14 checks passed
@whitequark whitequark deleted the assign-names branch November 25, 2023 06:32
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
None yet
Development

Successfully merging this pull request may close these issues.

1 participant