Fix paths issues and tcl commands

analogdevicesinc · Sep 28, 2023 · b92f789 · b92f789
1 parent 3f21897
commit b92f789
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Showing 4 changed files with 7 additions and 7 deletions.
diff --git a/...eting/cn0585_fmcz/+AnalogDevicesDemo/+cn0585_led_sw_gpio_control_demo/+common/plugin_rd.m b/...eting/cn0585_fmcz/+AnalogDevicesDemo/+cn0585_led_sw_gpio_control_demo/+common/plugin_rd.m
@@ -51,7 +51,7 @@
 
 %% Add custom design files
 hRD.addCustomVivadoDesign( ...
-    'CustomBlockDesignTcl', fullfile('hdl','vendor','AnalogDevices','vivado','projects','scripts', 'system_project_rxtx.tcl'));
+    'CustomBlockDesignTcl', fullfile('pcx_examples', 'targeting', 'cn0585_fmcz', 'cn0585_hdl', 'system_project_rxtx.tcl'));
 
 %% Standard reference design pieces
 hRD.BlockDesignName = 'system';

diff --git a/pcx_examples/targeting/cn0585_fmcz/cn0585_hdl/build_bsp.sh b/pcx_examples/targeting/cn0585_fmcz/cn0585_hdl/build_bsp.sh
@@ -78,7 +78,7 @@ cp ../../../../CI/ports.json ../../../../hdl/vendor/AnalogDevices/+AnalogDevices
 
 # Updates
 cp ./matlab_processors.tcl ../../../../hdl/vendor/AnalogDevices/vivado/projects/scripts/matlab_processors.tcl
-cp ../../../../CI/scripts/system_project_rxtx.tcl ../../../../hdl/vendor/AnalogDevices/vivado/projects/scripts/system_project_rxtx.tcl
+cp ./system_project_rxtx.tcl ../../../../hdl/vendor/AnalogDevices/vivado/projects/scripts/system_project_rxtx.tcl
 cp ./adi_build.tcl ../../../../hdl/vendor/AnalogDevices/vivado/projects/scripts/adi_build.tcl
 
 # Copy boot files

diff --git a/pcx_examples/targeting/cn0585_fmcz/cn0585_hdl/matlab_processors.tcl b/pcx_examples/targeting/cn0585_fmcz/cn0585_hdl/matlab_processors.tcl
@@ -3,7 +3,7 @@ proc preprocess_bd {project carrier rxtx} {
     puts "Preprocessing $project $carrier $rxtx"
 
     switch $project {
-        cn0585 {
+        cn0585_fmcz {
             # Disconnect the ADC PACK pins
             delete_bd_objs [get_bd_nets axi_ltc2387_0_adc_data]
 	        delete_bd_objs [get_bd_nets axi_ltc2387_1_adc_data]
@@ -75,6 +75,7 @@ proc preprocess_bd {project carrier rxtx} {
             connect_bd_net [get_bd_ports gpio_i] [get_bd_pins xlslice_1/Din]
             connect_bd_net [get_bd_ports gpio_i] [get_bd_pins xlslice_2/Din]
             create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_0
+	    set_property CONFIG.NUM_PORTS {3} [get_bd_cells xlconcat_0]
             set_property -dict [list CONFIG.IN2_WIDTH.VALUE_SRC USER CONFIG.IN1_WIDTH.VALUE_SRC USER CONFIG.IN0_WIDTH.VALUE_SRC USER] [get_bd_cells xlconcat_0]
             set_property -dict [list \
               CONFIG.IN0_WIDTH {45} \
@@ -112,6 +113,7 @@ proc preprocess_bd {project carrier rxtx} {
             connect_bd_net [get_bd_pins sys_ps7/GPIO_O] [get_bd_pins xlslice_4/Din]
             connect_bd_net [get_bd_pins sys_ps7/GPIO_O] [get_bd_pins xlslice_5/Din]
             create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_1
+	    set_property CONFIG.NUM_PORTS {3} [get_bd_cells xlconcat_1]
             set_property -dict [list CONFIG.IN2_WIDTH.VALUE_SRC USER CONFIG.IN1_WIDTH.VALUE_SRC USER CONFIG.IN0_WIDTH.VALUE_SRC USER] [get_bd_cells xlconcat_1]
             set_property -dict [list \
               CONFIG.IN0_WIDTH {37} \

diff --git a/pcx_examples/targeting/cn0585_fmcz/cn0585_hdl/system_project_rxtx.tcl b/pcx_examples/targeting/cn0585_fmcz/cn0585_hdl/system_project_rxtx.tcl
@@ -5,7 +5,6 @@ if {$preprocess == "on"} {
     source $preprocess_script
 }
 
-cd ../../../../hdl/vendor/AnalogDevices/vivado
 cd projects/$project/$carrier
 source ../../scripts/adi_make.tcl
 adi_make::lib all
@@ -19,9 +18,8 @@ set ::env(ADI_IGNORE_VERSION_CHECK) 1
 
 source ./system_project.tcl
 
-cd $start_dir
 # Update block design to make room for new IP
-source ./matlab_processors.tcl
+source ../../scripts/matlab_processors.tcl
 preprocess_bd $project $carrier $ref_design
 
 if {$postprocess == "on"} {
@@ -34,4 +32,4 @@ save_bd_design
 validate_bd_design
 
 # Back to root
-cd $start_dir
+cd $start_dir