-
Notifications
You must be signed in to change notification settings - Fork 31
Commit
This commit does not belong to any branch on this repository, and may belong to a fork outside of the repository.
Signed-off-by: Travis F. Collins <[email protected]>
- Loading branch information
Showing
9 changed files
with
1,265 additions
and
1 deletion.
There are no files selected for viewing
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
201 changes: 201 additions & 0 deletions
201
.../frequency-hopping/+AnalogDevicesDemo/+adrv9361z7035/+ccbob_lvds_hop/+rxtx/add_rx_tx_io.m
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,201 @@ | ||
| function add_rx_tx_io(hRD) | ||
|
|
||
| % add AXI4 and AXI4-Lite slave interfaces | ||
| hRD.addAXI4SlaveInterface( ... | ||
| 'InterfaceConnection', 'axi_cpu_interconnect/M06_AXI', ... | ||
| 'BaseAddress', '0x43C00000', ... | ||
| 'MasterAddressSpace', 'sys_ps7/Data'); | ||
|
|
||
| % % AGC control input for transceiver | ||
| % hRD.addInternalIOInterface( ... | ||
| % 'InterfaceID', 'Enable AGC', ... | ||
| % 'InterfaceType', 'OUT', ... | ||
| % 'PortName', 'en_agc', ... | ||
| % 'PortWidth', 1, ... | ||
| % 'InterfaceConnection', 'gpio_en_agc', ... | ||
| % 'IsRequired', false); | ||
|
|
||
| % GPIO status output for transceiver | ||
| hRD.addInternalIOInterface( ... | ||
| 'InterfaceID', 'CTRL_STATUS', ... | ||
| 'InterfaceType', 'IN', ... | ||
| 'PortName', 'gpio_status', ... | ||
| 'PortWidth', 8, ... | ||
| 'InterfaceConnection', 'gpio_status', ... | ||
| 'IsRequired', false); | ||
|
|
||
| % GPIO Control input for transceiver | ||
| hRD.addInternalIOInterface( ... | ||
| 'InterfaceID', 'AD9361 CTRL IN', ... | ||
| 'InterfaceType', 'OUT', ... | ||
| 'PortName', 'gpio_ctl', ... | ||
| 'PortWidth', 4, ... | ||
| 'InterfaceConnection', 'gpio_ctl', ... | ||
| 'IsRequired', false); | ||
|
|
||
| % DMA Ready signal | ||
| hRD.addInternalIOInterface( ... | ||
| 'InterfaceID', 'DMA Ready', ... | ||
| 'InterfaceType', 'IN', ... | ||
| 'PortName', 'dma_rdy', ... | ||
| 'PortWidth', 1, ... | ||
| 'InterfaceConnection', 'axi_ad9361_adc_dma/s_axis_ready', ... | ||
| 'IsRequired', false); | ||
|
|
||
| %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% | ||
| % Rx Reference design interfaces | ||
| %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% | ||
| hRD.addInternalIOInterface( ... | ||
| 'InterfaceID', 'IP Data Valid OUT', ... | ||
| 'InterfaceType', 'OUT', ... | ||
| 'PortName', 'dut_data_valid', ... | ||
| 'PortWidth', 1, ... | ||
| 'InterfaceConnection', 'util_ad9361_adc_pack/fifo_wr_en', ... | ||
| 'IsRequired', false); | ||
|
|
||
| hRD.addInternalIOInterface( ... | ||
| 'InterfaceID', 'IP Data 0 OUT', ... | ||
| 'InterfaceType', 'OUT', ... | ||
| 'PortName', 'dut_data_0', ... | ||
| 'PortWidth', 16, ... | ||
| 'InterfaceConnection', 'util_ad9361_adc_pack/fifo_wr_data_0', ... | ||
| 'IsRequired', false); | ||
|
|
||
| hRD.addInternalIOInterface( ... | ||
| 'InterfaceID', 'IP Data 1 OUT', ... | ||
| 'InterfaceType', 'OUT', ... | ||
| 'PortName', 'dut_data_1', ... | ||
| 'PortWidth', 16, ... | ||
| 'InterfaceConnection', 'util_ad9361_adc_pack/fifo_wr_data_1', ... | ||
| 'IsRequired', false); | ||
|
|
||
| % hRD.addInternalIOInterface( ... | ||
| % 'InterfaceID', 'IP Data 2 OUT', ... | ||
| % 'InterfaceType', 'OUT', ... | ||
| % 'PortName', 'dut_data_2', ... | ||
| % 'PortWidth', 16, ... | ||
| % 'InterfaceConnection', 'util_ad9361_adc_pack/fifo_wr_data_2', ... | ||
| % 'IsRequired', false); | ||
|
|
||
| % hRD.addInternalIOInterface( ... | ||
| % 'InterfaceID', 'IP Data 3 OUT', ... | ||
| % 'InterfaceType', 'OUT', ... | ||
| % 'PortName', 'dut_data_3', ... | ||
| % 'PortWidth', 16, ... | ||
| % 'InterfaceConnection', 'util_ad9361_adc_pack/fifo_wr_data_3', ... | ||
| % 'IsRequired', false); | ||
|
|
||
| hRD.addInternalIOInterface( ... | ||
| 'InterfaceID', 'AD9361 ADC Data I0', ... | ||
| 'InterfaceType', 'IN', ... | ||
| 'PortName', 'sys_wfifo_0_dma_wdata', ... | ||
| 'PortWidth', 16, ... | ||
| 'InterfaceConnection', 'util_ad9361_adc_fifo/dout_data_0', ... | ||
| 'IsRequired', false); | ||
|
|
||
| hRD.addInternalIOInterface( ... | ||
| 'InterfaceID', 'AD9361 ADC Data Q0', ... | ||
| 'InterfaceType', 'IN', ... | ||
| 'PortName', 'sys_wfifo_1_dma_wdata', ... | ||
| 'PortWidth', 16, ... | ||
| 'InterfaceConnection', 'util_ad9361_adc_fifo/dout_data_1', ... | ||
| 'IsRequired', false); | ||
|
|
||
| % hRD.addInternalIOInterface( ... | ||
| % 'InterfaceID', 'AD9361 ADC Data I1', ... | ||
| % 'InterfaceType', 'IN', ... | ||
| % 'PortName', 'sys_wfifo_2_dma_wdata', ... | ||
| % 'PortWidth', 16, ... | ||
| % 'InterfaceConnection', 'util_ad9361_adc_fifo/dout_data_2', ... | ||
| % 'IsRequired', false); | ||
|
|
||
| % hRD.addInternalIOInterface( ... | ||
| % 'InterfaceID', 'AD9361 ADC Data Q1', ... | ||
| % 'InterfaceType', 'IN', ... | ||
| % 'PortName', 'sys_wfifo_3_dma_wdata', ... | ||
| % 'PortWidth', 16, ... | ||
| % 'InterfaceConnection', 'util_ad9361_adc_fifo/dout_data_3', ... | ||
| % 'IsRequired', false); | ||
|
|
||
| %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% | ||
| % Tx Reference design interfaces | ||
| %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% | ||
| hRD.addInternalIOInterface( ... | ||
| 'InterfaceID', 'AD9361 DAC Data I0', ... | ||
| 'InterfaceType', 'OUT', ... | ||
| 'PortName', 'axi_ad9361_dac_data_i0', ... | ||
| 'PortWidth', 16, ... | ||
| 'InterfaceConnection', 'axi_ad9361_dac_fifo/din_data_0', ... | ||
| 'IsRequired', false); | ||
|
|
||
| hRD.addInternalIOInterface( ... | ||
| 'InterfaceID', 'AD9361 DAC Data Q0', ... | ||
| 'InterfaceType', 'OUT', ... | ||
| 'PortName', 'axi_ad9361_dac_data_q0', ... | ||
| 'PortWidth', 16, ... | ||
| 'InterfaceConnection', 'axi_ad9361_dac_fifo/din_data_1', ... | ||
| 'IsRequired', false); | ||
|
|
||
| % hRD.addInternalIOInterface( ... | ||
| % 'InterfaceID', 'AD9361 DAC Data I1', ... | ||
| % 'InterfaceType', 'OUT', ... | ||
| % 'PortName', 'axi_ad9361_dac_data_i1', ... | ||
| % 'PortWidth', 16, ... | ||
| % 'InterfaceConnection', 'axi_ad9361_dac_fifo/din_data_2', ... | ||
| % 'IsRequired', false); | ||
|
|
||
| % hRD.addInternalIOInterface( ... | ||
| % 'InterfaceID', 'AD9361 DAC Data Q1', ... | ||
| % 'InterfaceType', 'OUT', ... | ||
| % 'PortName', 'axi_ad9361_dac_data_q1', ... | ||
| % 'PortWidth', 16, ... | ||
| % 'InterfaceConnection', 'axi_ad9361_dac_fifo/din_data_3', ... | ||
| % 'IsRequired', false); | ||
|
|
||
| hRD.addInternalIOInterface( ... | ||
| 'InterfaceID', 'IP Data 0 IN', ... | ||
| 'InterfaceType', 'IN', ... | ||
| 'PortName', 'util_dac_unpack_dac_data_00', ... | ||
| 'PortWidth', 16, ... | ||
| 'InterfaceConnection', 'util_ad9361_dac_upack/fifo_rd_data_0', ... | ||
| 'IsRequired', false); | ||
|
|
||
| hRD.addInternalIOInterface( ... | ||
| 'InterfaceID', 'IP Data 1 IN', ... | ||
| 'InterfaceType', 'IN', ... | ||
| 'PortName', 'util_dac_unpack_dac_data_01', ... | ||
| 'PortWidth', 16, ... | ||
| 'InterfaceConnection', 'util_ad9361_dac_upack/fifo_rd_data_1', ... | ||
| 'IsRequired', false); | ||
|
|
||
| % hRD.addInternalIOInterface( ... | ||
| % 'InterfaceID', 'IP Data 2 IN', ... | ||
| % 'InterfaceType', 'IN', ... | ||
| % 'PortName', 'util_dac_unpack_dac_data_02', ... | ||
| % 'PortWidth', 16, ... | ||
| % 'InterfaceConnection', 'util_ad9361_dac_upack/fifo_rd_data_2', ... | ||
| % 'IsRequired', false); | ||
|
|
||
| % hRD.addInternalIOInterface( ... | ||
| % 'InterfaceID', 'IP Data 3 IN', ... | ||
| % 'InterfaceType', 'IN', ... | ||
| % 'PortName', 'util_dac_unpack_dac_data_03', ... | ||
| % 'PortWidth', 16, ... | ||
| % 'InterfaceConnection', 'util_ad9361_dac_upack/fifo_rd_data_3', ... | ||
| % 'IsRequired', false); | ||
|
|
||
| hRD.addInternalIOInterface( ... | ||
| 'InterfaceID', 'IP Load Tx Data OUT', ... | ||
| 'InterfaceType', 'OUT', ... | ||
| 'PortName', 'util_dac_unpack_dac_valid_00', ... | ||
| 'PortWidth', 1, ... | ||
| 'InterfaceConnection', 'util_ad9361_dac_upack/din_valid_in_0', ... | ||
| 'IsRequired', false); | ||
|
|
||
| hRD.addInternalIOInterface( ... | ||
| 'InterfaceID', 'IP Valid Tx Data IN', ... | ||
| 'InterfaceType', 'IN', ... | ||
| 'PortName', 'util_dac_unpack_upack_valid_00', ... | ||
| 'PortWidth', 1, ... | ||
| 'InterfaceConnection', 'util_ad9361_dac_upack/fifo_rd_valid', ... | ||
| 'IsRequired', false); |
18 changes: 18 additions & 0 deletions
18
...nalogDevicesDemo/+adrv9361z7035/+ccbob_lvds_hop/+rxtx/hdlcoder_ref_design_customization.m
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,18 @@ | ||
| function [rd, boardName] = hdlcoder_ref_design_customization | ||
| % Reference design plugin registration file | ||
| % 1. The registration file with this name inside of a board plugin folder | ||
| % will be picked up | ||
| % 2. Any registration file with this name on MATLAB path will also be picked up | ||
| % 3. The registration file returns a cell array pointing to the location of | ||
| % the reference design plugins | ||
| % 4. The registration file also returns its associated board name | ||
| % 5. Reference design plugin must be a package folder accessible from | ||
| % MATLAB path, and contains a reference design definition file | ||
|
|
||
| rd = {'AnalogDevicesDemo.adrv9364z7020.ccbob_lvds_hop.rxtx.plugin_rd', ... | ||
| }; | ||
|
|
||
| boardName = 'AnalogDevicesDemo adrv9364z7020 bob lvds hop (Rx & Tx)'; | ||
|
|
||
| end | ||
|
|
7 changes: 7 additions & 0 deletions
7
.../frequency-hopping/+AnalogDevicesDemo/+adrv9361z7035/+ccbob_lvds_hop/+rxtx/plugin_board.m
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,7 @@ | ||
| function hP = plugin_board() | ||
| % Zynq Platform PCore | ||
| % Use Plugin API to create board plugin object | ||
|
|
||
| % Call the common board definition function | ||
| hP = AnalogDevices.adrv9364z7020.common.plugin_board('bob lvds hop', 'Rx & Tx'); | ||
|
|
8 changes: 8 additions & 0 deletions
8
...ing/frequency-hopping/+AnalogDevicesDemo/+adrv9361z7035/+ccbob_lvds_hop/+rxtx/plugin_rd.m
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,8 @@ | ||
| function hRD = plugin_rd | ||
| % Reference design definition | ||
|
|
||
| % Copyright 2014-2015 The MathWorks, Inc. | ||
|
|
||
| % Call the common reference design definition function | ||
| hRD = AnalogDevicesDemo.adrv9364z7020.common.plugin_rd('ccbob_lvds_hop', 'Rx & Tx'); | ||
| AnalogDevicesDemo.adrv9364z7020.ccbob_lvds_hop.rxtx.add_rx_tx_io(hRD); |
14 changes: 14 additions & 0 deletions
14
trx_examples/targeting/frequency-hopping/ccbob_lvds_hop/fh_preprocess.tcl
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,14 @@ | ||
| set ad_hdl_dir [pwd] | ||
|
|
||
| #### Move files | ||
| file rename -force $ad_hdl_dir/hdl/vendor/AnalogDevices/vivado/scripts $ad_hdl_dir/scripts | ||
| file rename -force $ad_hdl_dir/hdl/vendor/AnalogDevices/vivado/projects $ad_hdl_dir/projects | ||
| file rename -force $ad_hdl_dir/hdl/vendor/AnalogDevices/vivado/library $ad_hdl_dir/library | ||
| file copy -force $ad_hdl_dir/trx_examples/targeting/frequency-hopping/ccbob_lvds_hop/system_top.v $ad_hdl_dir/projects/adrv9364z7020/ccbob_lvds/system_top.v | ||
| set f [open $ad_hdl_dir/projects/adrv9364z7020/ccbob_lvds/system_bd.tcl "a"] | ||
|
|
||
| # To check | ||
| puts $f "create_bd_port -dir O gpio_en_agc" | ||
| puts $f "create_bd_port -from 0 -to 7 -dir I gpio_status" | ||
| puts $f "create_bd_port -from 0 -to 3 -dir O gpio_ctl" | ||
| close $f |
Oops, something went wrong.