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Update Zephyr MSDK Hal based on MSDK PR: analogdevicesinc/msdk#1079
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@actions-user @ttmut
actions-user authored and ttmut committed Oct 31, 2024
1 parent 3a270dc commit 652a04f
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Showing 98 changed files with 3,052 additions and 17,180 deletions.
2 changes: 1 addition & 1 deletion MAX/CMakeLists.txt
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Expand Up @@ -40,7 +40,7 @@ set(MSDK_PERIPH_INC_DIR ${MSDK_PERIPH_DIR}/Include/${TARGET_UC})

zephyr_include_directories(
./Include
./Source/${TARGET_UC}
${MSDK_LIBRARY_DIR}/CMSIS/Include
${MSDK_CMSIS_DIR}/Include
${MSDK_PERIPH_INC_DIR}
)
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20 changes: 2 additions & 18 deletions MAX/Include/wrap_max32_spi.h
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Expand Up @@ -76,20 +76,14 @@ static inline int Wrap_MXC_SPI_Init(mxc_spi_regs_t *spi, int masterMode, int qua
#elif defined(CONFIG_SOC_MAX32690) || (CONFIG_SOC_MAX32655) || (CONFIG_SOC_MAX32670) || \
(CONFIG_SOC_MAX32672) || (CONFIG_SOC_MAX32662) || (CONFIG_SOC_MAX32675) || \
(CONFIG_SOC_MAX32680) || (CONFIG_SOC_MAX32657)
#if defined(CONFIG_SOC_MAX32657)
#define ADI_MAX32_SPI_CTRL_MASTER_MODE MXC_F_SPI_CTRL0_CONT_MODE
#else

#define ADI_MAX32_SPI_CTRL_MASTER_MODE MXC_F_SPI_CTRL0_MST_MODE
#endif

#define ADI_MAX32_SPI_INT_FL_RX_UN MXC_F_SPI_INTFL_RX_UN
#define ADI_MAX32_SPI_INT_FL_RX_OV MXC_F_SPI_INTFL_RX_OV
#define ADI_MAX32_SPI_INT_FL_TX_UN MXC_F_SPI_INTFL_TX_UN
#define ADI_MAX32_SPI_INT_FL_TX_OV MXC_F_SPI_INTFL_TX_OV
#if defined(CONFIG_SOC_MAX32657)
#define ADI_MAX32_SPI_INT_FL_MST_DONE MXC_F_SPI_INTFL_CONT_DONE
#else
#define ADI_MAX32_SPI_INT_FL_MST_DONE MXC_F_SPI_INTFL_MST_DONE
#endif
#define ADI_MAX32_SPI_INT_FL_ABORT MXC_F_SPI_INTFL_ABORT
#define ADI_MAX32_SPI_INT_FL_FAULT MXC_F_SPI_INTFL_FAULT
#define ADI_MAX32_SPI_INT_FL_SSD MXC_F_SPI_INTFL_SSD
Expand All @@ -102,11 +96,7 @@ static inline int Wrap_MXC_SPI_Init(mxc_spi_regs_t *spi, int masterMode, int qua
#define ADI_MAX32_SPI_INT_EN_RX_OV MXC_F_SPI_INTEN_RX_OV
#define ADI_MAX32_SPI_INT_EN_TX_UN MXC_F_SPI_INTEN_TX_UN
#define ADI_MAX32_SPI_INT_EN_TX_OV MXC_F_SPI_INTEN_TX_OV
#if defined(CONFIG_SOC_MAX32657)
#define ADI_MAX32_SPI_INT_EN_MST_DONE MXC_F_SPI_INTEN_CONT_DONE
#else
#define ADI_MAX32_SPI_INT_EN_MST_DONE MXC_F_SPI_INTEN_MST_DONE
#endif
#define ADI_MAX32_SPI_INT_EN_ABORT MXC_F_SPI_INTEN_ABORT
#define ADI_MAX32_SPI_INT_EN_FAULT MXC_F_SPI_INTEN_FAULT
#define ADI_MAX32_SPI_INT_EN_SSD MXC_F_SPI_INTEN_SSD
Expand Down Expand Up @@ -138,12 +128,6 @@ static inline int Wrap_MXC_SPI_Init(mxc_spi_regs_t *spi, int masterMode, int qua

#endif // part number

#if defined(CONFIG_SOC_MAX32657)
#define ADI_MAX32_SPI_CTRL0_SS_CTRL MXC_F_SPI_CTRL0_TS_CTRL
#else
#define ADI_MAX32_SPI_CTRL0_SS_CTRL MXC_F_SPI_CTRL0_SS_CTRL
#endif

#ifdef __cplusplus
}
#endif
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4 changes: 0 additions & 4 deletions MAX/Include/wrap_max32_sys.h
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Expand Up @@ -69,8 +69,6 @@ static inline void Wrap_MXC_SYS_SetClockDiv(int div)
#define ADI_MAX32_CLK_ISO MXC_SYS_CLOCK_ISO
#endif

#if !defined(CONFIG_SOC_MAX32690)

#define z_sysclk_prescaler(v) MXC_SYS_CLOCK_DIV_##v
#define sysclk_prescaler(v) z_sysclk_prescaler(v)

Expand All @@ -79,8 +77,6 @@ static inline void Wrap_MXC_SYS_SetClockDiv(int div)
MXC_SYS_SetClockDiv((mxc_sys_system_clock_div_t)div);
}

#endif // !defined(CONFIG_SOC_MAX32690)

#endif // part number

#ifdef __cplusplus
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2 changes: 1 addition & 1 deletion MAX/Include/wrap_max32_tmr.h
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Expand Up @@ -105,7 +105,7 @@ int Wrap_MXC_TMR_GetPendingInt(mxc_tmr_regs_t *tmr)
(CONFIG_SOC_MAX32672) || (CONFIG_SOC_MAX32662) || (CONFIG_SOC_MAX32675) || \
(CONFIG_SOC_MAX32680) || (CONFIG_SOC_MAX32657)

#if defined(CONFIG_SOC_MAX32672) || (CONFIG_SOC_MAX32675) || (CONFIG_SOC_MAX32657)
#if defined(CONFIG_SOC_MAX32672) || (CONFIG_SOC_MAX32675)
/* All timers are 32bits */
#define WRAP_MXC_IS_32B_TIMER(idx) (1)
#elif defined(CONFIG_SOC_MAX32662)
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6 changes: 1 addition & 5 deletions MAX/Include/wrap_max32_uart.h
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Expand Up @@ -133,11 +133,7 @@ static inline void Wrap_MXC_UART_DisableRxDMA(mxc_uart_regs_t *uart)
#define ADI_MAX32_UART_INT_OE MXC_F_UART_INTEN_RX_OV // Overrun Error Interrupt
#define ADI_MAX32_UART_INT_PE MXC_F_UART_INTEN_RX_PAR // Parity Error Interrupt
#define ADI_MAX32_UART_INT_FE MXC_F_UART_INTEN_RX_FERR // Framing Error Interrupt
#if defined(CONFIG_SOC_MAX32657)
#define ADI_MAX32_UART_INT_TX MXC_F_UART_INTEN_TX_THD // Transmit Interrupt
#else
#define ADI_MAX32_UART_INT_TX MXC_F_UART_INTEN_TX_HE // Transmit Interrupt
#endif
#define ADI_MAX32_UART_INT_RX MXC_F_UART_INTEN_RX_THD // Receive Interrupt
#define ADI_MAX32_UART_INT_CTS MXC_F_UART_INTEN_CTS_EV // CTS Modem Interrupt
#define ADI_MAX32_UART_INT_TX_OEM MXC_F_UART_INTEN_TX_OB // TX FIFO Almost Empty Interrupt
Expand Down Expand Up @@ -219,7 +215,7 @@ static inline void Wrap_MXC_UART_DisableRxDMA(mxc_uart_regs_t *uart)

static inline unsigned int Wrap_MXC_UART_GetRegINTEN(mxc_uart_regs_t *uart)
{
#if defined(CONFIG_SOC_MAX32662) || (CONFIG_SOC_MAX32657)
#if defined(CONFIG_SOC_MAX32662)
return uart->inten;
#else
return uart->int_en;
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220 changes: 0 additions & 220 deletions MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/boost_regs.h
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This file was deleted.

1 change: 1 addition & 0 deletions MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/crc_regs.h
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Expand Up @@ -78,6 +78,7 @@ typedef struct {
__IO uint16_t datain16; /**< <tt>\b 0x0004:</tt> CRC DATAIN16 Register */
__IO uint8_t datain8; /**< <tt>\b 0x0004:</tt> CRC DATAIN8 Register */
};
__R uint8_t rsv_0x5_0x7[3];
__IO uint32_t poly; /**< <tt>\b 0x0008:</tt> CRC POLY Register */
__IO uint32_t val; /**< <tt>\b 0x000C:</tt> CRC VAL Register */
} mxc_crc_regs_t;
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20 changes: 8 additions & 12 deletions MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/dma_regs.h
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Expand Up @@ -176,26 +176,22 @@ typedef struct {
#define MXC_F_DMA_CTRL_REQUEST ((uint32_t)(0x3FUL << MXC_F_DMA_CTRL_REQUEST_POS)) /**< CTRL_REQUEST Mask */
#define MXC_V_DMA_CTRL_REQUEST_MEMTOMEM ((uint32_t)0x0UL) /**< CTRL_REQUEST_MEMTOMEM Value */
#define MXC_S_DMA_CTRL_REQUEST_MEMTOMEM (MXC_V_DMA_CTRL_REQUEST_MEMTOMEM << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_MEMTOMEM Setting */
#define MXC_V_DMA_CTRL_REQUEST_SPIRX ((uint32_t)0x1UL) /**< CTRL_REQUEST_SPIRX Value */
#define MXC_S_DMA_CTRL_REQUEST_SPIRX (MXC_V_DMA_CTRL_REQUEST_SPIRX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_SPIRX Setting */
#define MXC_V_DMA_CTRL_REQUEST_UARTRX ((uint32_t)0x4UL) /**< CTRL_REQUEST_UARTRX Value */
#define MXC_S_DMA_CTRL_REQUEST_UARTRX (MXC_V_DMA_CTRL_REQUEST_UARTRX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_UARTRX Setting */
#define MXC_V_DMA_CTRL_REQUEST_I3CRX_CONT ((uint32_t)0x7UL) /**< CTRL_REQUEST_I3CRX_CONT Value */
#define MXC_S_DMA_CTRL_REQUEST_I3CRX_CONT (MXC_V_DMA_CTRL_REQUEST_I3CRX_CONT << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_I3CRX_CONT Setting */
#define MXC_V_DMA_CTRL_REQUEST_I3CRX_TARG ((uint32_t)0x8UL) /**< CTRL_REQUEST_I3CRX_TARG Value */
#define MXC_S_DMA_CTRL_REQUEST_I3CRX_TARG (MXC_V_DMA_CTRL_REQUEST_I3CRX_TARG << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_I3CRX_TARG Setting */
#define MXC_V_DMA_CTRL_REQUEST_I3CRX ((uint32_t)0x7UL) /**< CTRL_REQUEST_I3CRX Value */
#define MXC_S_DMA_CTRL_REQUEST_I3CRX (MXC_V_DMA_CTRL_REQUEST_I3CRX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_I3CRX Setting */
#define MXC_V_DMA_CTRL_REQUEST_SPIRX ((uint32_t)0xFUL) /**< CTRL_REQUEST_SPIRX Value */
#define MXC_S_DMA_CTRL_REQUEST_SPIRX (MXC_V_DMA_CTRL_REQUEST_SPIRX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_SPIRX Setting */
#define MXC_V_DMA_CTRL_REQUEST_AESRX ((uint32_t)0x10UL) /**< CTRL_REQUEST_AESRX Value */
#define MXC_S_DMA_CTRL_REQUEST_AESRX (MXC_V_DMA_CTRL_REQUEST_AESRX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_AESRX Setting */
#define MXC_V_DMA_CTRL_REQUEST_SPITX ((uint32_t)0x21UL) /**< CTRL_REQUEST_SPITX Value */
#define MXC_S_DMA_CTRL_REQUEST_SPITX (MXC_V_DMA_CTRL_REQUEST_SPITX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_SPITX Setting */
#define MXC_V_DMA_CTRL_REQUEST_UARTTX ((uint32_t)0x24UL) /**< CTRL_REQUEST_UARTTX Value */
#define MXC_S_DMA_CTRL_REQUEST_UARTTX (MXC_V_DMA_CTRL_REQUEST_UARTTX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_UARTTX Setting */
#define MXC_V_DMA_CTRL_REQUEST_I3CTX_CONT ((uint32_t)0x27UL) /**< CTRL_REQUEST_I3CTX_CONT Value */
#define MXC_S_DMA_CTRL_REQUEST_I3CTX_CONT (MXC_V_DMA_CTRL_REQUEST_I3CTX_CONT << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_I3CTX_CONT Setting */
#define MXC_V_DMA_CTRL_REQUEST_I3CTX_TARG ((uint32_t)0x28UL) /**< CTRL_REQUEST_I3CTX_TARG Value */
#define MXC_S_DMA_CTRL_REQUEST_I3CTX_TARG (MXC_V_DMA_CTRL_REQUEST_I3CTX_TARG << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_I3CTX_TARG Setting */
#define MXC_V_DMA_CTRL_REQUEST_I3CTX ((uint32_t)0x27UL) /**< CTRL_REQUEST_I3CTX Value */
#define MXC_S_DMA_CTRL_REQUEST_I3CTX (MXC_V_DMA_CTRL_REQUEST_I3CTX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_I3CTX Setting */
#define MXC_V_DMA_CTRL_REQUEST_CRCTX ((uint32_t)0x2CUL) /**< CTRL_REQUEST_CRCTX Value */
#define MXC_S_DMA_CTRL_REQUEST_CRCTX (MXC_V_DMA_CTRL_REQUEST_CRCTX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_CRCTX Setting */
#define MXC_V_DMA_CTRL_REQUEST_SPITX ((uint32_t)0x2FUL) /**< CTRL_REQUEST_SPITX Value */
#define MXC_S_DMA_CTRL_REQUEST_SPITX (MXC_V_DMA_CTRL_REQUEST_SPITX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_SPITX Setting */
#define MXC_V_DMA_CTRL_REQUEST_AESTX ((uint32_t)0x30UL) /**< CTRL_REQUEST_AESTX Value */
#define MXC_S_DMA_CTRL_REQUEST_AESTX (MXC_V_DMA_CTRL_REQUEST_AESTX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_AESTX Setting */

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