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Update Zephyr MSDK Hal based on MSDK PR: analogdevicesinc/msdk#1242
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@actions-user @ttmut
actions-user authored and ttmut committed Oct 31, 2024
1 parent 734a757 commit becead8
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Showing 29 changed files with 3,492 additions and 617 deletions.
3 changes: 1 addition & 2 deletions MAX/Include/wrap_max32_tmr.h
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Original file line number Diff line number Diff line change
Expand Up @@ -105,8 +105,7 @@ int Wrap_MXC_TMR_GetPendingInt(mxc_tmr_regs_t *tmr)
(CONFIG_SOC_MAX32672) || (CONFIG_SOC_MAX32662) || (CONFIG_SOC_MAX32675) || \
(CONFIG_SOC_MAX32680) || (CONFIG_SOC_MAX32657) || (CONFIG_SOC_MAX78002)

#if defined(CONFIG_SOC_MAX32672) || (CONFIG_SOC_MAX32675) || (CONFIG_SOC_MAX32657) || \
(CONFIG_SOC_MAX32670)
#if defined(CONFIG_SOC_MAX32672) || (CONFIG_SOC_MAX32675) || (CONFIG_SOC_MAX32657)
/* All timers are 32bits */
#define WRAP_MXC_IS_32B_TIMER(idx) (1)
#elif defined(CONFIG_SOC_MAX32662)
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20 changes: 1 addition & 19 deletions MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/fcr_regs.h
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Original file line number Diff line number Diff line change
Expand Up @@ -80,7 +80,7 @@ typedef struct {
__IO uint32_t erfoks; /**< <tt>\b 0x18:</tt> FCR ERFOKS Register */
__IO uint32_t intfl; /**< <tt>\b 0x1C:</tt> FCR INTFL Register */
__IO uint32_t inten; /**< <tt>\b 0x20:</tt> FCR INTEN Register */
__IO uint32_t erfoctrl; /**< <tt>\b 0x24:</tt> FCR ERFOCTRL Register */
__R uint32_t rsv_0x24;
__IO uint32_t frqcntctrl; /**< <tt>\b 0x28:</tt> FCR FRQCNTCTRL Register */
__IO uint32_t frqcntcmp; /**< <tt>\b 0x2C:</tt> FCR FRQCNTCMP Register */
__I uint32_t refclk; /**< <tt>\b 0x30:</tt> FCR REFCLK Register */
Expand All @@ -101,7 +101,6 @@ typedef struct {
#define MXC_R_FCR_ERFOKS ((uint32_t)0x00000018UL) /**< Offset from FCR Base Address: <tt> 0x0018</tt> */
#define MXC_R_FCR_INTFL ((uint32_t)0x0000001CUL) /**< Offset from FCR Base Address: <tt> 0x001C</tt> */
#define MXC_R_FCR_INTEN ((uint32_t)0x00000020UL) /**< Offset from FCR Base Address: <tt> 0x0020</tt> */
#define MXC_R_FCR_ERFOCTRL ((uint32_t)0x00000024UL) /**< Offset from FCR Base Address: <tt> 0x0024</tt> */
#define MXC_R_FCR_FRQCNTCTRL ((uint32_t)0x00000028UL) /**< Offset from FCR Base Address: <tt> 0x0028</tt> */
#define MXC_R_FCR_FRQCNTCMP ((uint32_t)0x0000002CUL) /**< Offset from FCR Base Address: <tt> 0x002C</tt> */
#define MXC_R_FCR_REFCLK ((uint32_t)0x00000030UL) /**< Offset from FCR Base Address: <tt> 0x0030</tt> */
Expand Down Expand Up @@ -237,23 +236,6 @@ typedef struct {

/**@} end of group FCR_INTEN_Register */

/**
* @ingroup fcr_registers
* @defgroup FCR_ERFOCTRL FCR_ERFOCTRL
* @brief ERFO Control Register.
* @{
*/
#define MXC_F_FCR_ERFOCTRL_CAP_X1_POS 0 /**< ERFOCTRL_CAP_X1 Position */
#define MXC_F_FCR_ERFOCTRL_CAP_X1 ((uint32_t)(0x7FUL << MXC_F_FCR_ERFOCTRL_CAP_X1_POS)) /**< ERFOCTRL_CAP_X1 Mask */

#define MXC_F_FCR_ERFOCTRL_CAP_X2_POS 7 /**< ERFOCTRL_CAP_X2 Position */
#define MXC_F_FCR_ERFOCTRL_CAP_X2 ((uint32_t)(0x7FUL << MXC_F_FCR_ERFOCTRL_CAP_X2_POS)) /**< ERFOCTRL_CAP_X2 Mask */

#define MXC_F_FCR_ERFOCTRL_CAP_BYPASS_POS 14 /**< ERFOCTRL_CAP_BYPASS Position */
#define MXC_F_FCR_ERFOCTRL_CAP_BYPASS ((uint32_t)(0x1UL << MXC_F_FCR_ERFOCTRL_CAP_BYPASS_POS)) /**< ERFOCTRL_CAP_BYPASS Mask */

/**@} end of group FCR_ERFOCTRL_Register */

/**
* @ingroup fcr_registers
* @defgroup FCR_FRQCNTCTRL FCR_FRQCNTCTRL
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48 changes: 24 additions & 24 deletions MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/gcr_regs.h
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Original file line number Diff line number Diff line change
Expand Up @@ -563,48 +563,48 @@ typedef struct {
* @brief BTLE LDO Control Register
* @{
*/
#define MXC_F_GCR_BTLELDOCTRL_BB_EN_POS 0 /**< BTLELDOCTRL_BB_EN Position */
#define MXC_F_GCR_BTLELDOCTRL_BB_EN ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_BB_EN_POS)) /**< BTLELDOCTRL_BB_EN Mask */

#define MXC_F_GCR_BTLELDOCTRL_BB_PD_EN_POS 1 /**< BTLELDOCTRL_BB_PD_EN Position */
#define MXC_F_GCR_BTLELDOCTRL_BB_PD_EN ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_BB_PD_EN_POS)) /**< BTLELDOCTRL_BB_PD_EN Mask */

#define MXC_F_GCR_BTLELDOCTRL_BB_VSEL_POS 2 /**< BTLELDOCTRL_BB_VSEL Position */
#define MXC_F_GCR_BTLELDOCTRL_BB_VSEL ((uint32_t)(0x3UL << MXC_F_GCR_BTLELDOCTRL_BB_VSEL_POS)) /**< BTLELDOCTRL_BB_VSEL Mask */

#define MXC_F_GCR_BTLELDOCTRL_RF_EN_POS 4 /**< BTLELDOCTRL_RF_EN Position */
#define MXC_F_GCR_BTLELDOCTRL_RF_EN_POS 0 /**< BTLELDOCTRL_RF_EN Position */
#define MXC_F_GCR_BTLELDOCTRL_RF_EN ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_RF_EN_POS)) /**< BTLELDOCTRL_RF_EN Mask */

#define MXC_F_GCR_BTLELDOCTRL_RF_PD_EN_POS 5 /**< BTLELDOCTRL_RF_PD_EN Position */
#define MXC_F_GCR_BTLELDOCTRL_RF_PD_EN_POS 1 /**< BTLELDOCTRL_RF_PD_EN Position */
#define MXC_F_GCR_BTLELDOCTRL_RF_PD_EN ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_RF_PD_EN_POS)) /**< BTLELDOCTRL_RF_PD_EN Mask */

#define MXC_F_GCR_BTLELDOCTRL_RF_VSEL_POS 6 /**< BTLELDOCTRL_RF_VSEL Position */
#define MXC_F_GCR_BTLELDOCTRL_RF_VSEL_POS 2 /**< BTLELDOCTRL_RF_VSEL Position */
#define MXC_F_GCR_BTLELDOCTRL_RF_VSEL ((uint32_t)(0x3UL << MXC_F_GCR_BTLELDOCTRL_RF_VSEL_POS)) /**< BTLELDOCTRL_RF_VSEL Mask */

#define MXC_F_GCR_BTLELDOCTRL_RF_BP_EN_POS 8 /**< BTLELDOCTRL_RF_BP_EN Position */
#define MXC_F_GCR_BTLELDOCTRL_RF_BP_EN ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_RF_BP_EN_POS)) /**< BTLELDOCTRL_RF_BP_EN Mask */
#define MXC_F_GCR_BTLELDOCTRL_BB_EN_POS 4 /**< BTLELDOCTRL_BB_EN Position */
#define MXC_F_GCR_BTLELDOCTRL_BB_EN ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_BB_EN_POS)) /**< BTLELDOCTRL_BB_EN Mask */

#define MXC_F_GCR_BTLELDOCTRL_RF_DISCH_POS 9 /**< BTLELDOCTRL_RF_DISCH Position */
#define MXC_F_GCR_BTLELDOCTRL_RF_DISCH ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_RF_DISCH_POS)) /**< BTLELDOCTRL_RF_DISCH Mask */
#define MXC_F_GCR_BTLELDOCTRL_BB_PD_EN_POS 5 /**< BTLELDOCTRL_BB_PD_EN Position */
#define MXC_F_GCR_BTLELDOCTRL_BB_PD_EN ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_BB_PD_EN_POS)) /**< BTLELDOCTRL_BB_PD_EN Mask */

#define MXC_F_GCR_BTLELDOCTRL_BB_BP_EN_POS 10 /**< BTLELDOCTRL_BB_BP_EN Position */
#define MXC_F_GCR_BTLELDOCTRL_BB_VSEL_POS 6 /**< BTLELDOCTRL_BB_VSEL Position */
#define MXC_F_GCR_BTLELDOCTRL_BB_VSEL ((uint32_t)(0x3UL << MXC_F_GCR_BTLELDOCTRL_BB_VSEL_POS)) /**< BTLELDOCTRL_BB_VSEL Mask */

#define MXC_F_GCR_BTLELDOCTRL_BB_BP_EN_POS 8 /**< BTLELDOCTRL_BB_BP_EN Position */
#define MXC_F_GCR_BTLELDOCTRL_BB_BP_EN ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_BB_BP_EN_POS)) /**< BTLELDOCTRL_BB_BP_EN Mask */

#define MXC_F_GCR_BTLELDOCTRL_BB_DISCH_POS 11 /**< BTLELDOCTRL_BB_DISCH Position */
#define MXC_F_GCR_BTLELDOCTRL_BB_DISCH_POS 9 /**< BTLELDOCTRL_BB_DISCH Position */
#define MXC_F_GCR_BTLELDOCTRL_BB_DISCH ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_BB_DISCH_POS)) /**< BTLELDOCTRL_BB_DISCH Mask */

#define MXC_F_GCR_BTLELDOCTRL_BB_EN_DLY_POS 12 /**< BTLELDOCTRL_BB_EN_DLY Position */
#define MXC_F_GCR_BTLELDOCTRL_BB_EN_DLY ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_BB_EN_DLY_POS)) /**< BTLELDOCTRL_BB_EN_DLY Mask */
#define MXC_F_GCR_BTLELDOCTRL_RF_BP_EN_POS 10 /**< BTLELDOCTRL_RF_BP_EN Position */
#define MXC_F_GCR_BTLELDOCTRL_RF_BP_EN ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_RF_BP_EN_POS)) /**< BTLELDOCTRL_RF_BP_EN Mask */

#define MXC_F_GCR_BTLELDOCTRL_RF_DISCH_POS 11 /**< BTLELDOCTRL_RF_DISCH Position */
#define MXC_F_GCR_BTLELDOCTRL_RF_DISCH ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_RF_DISCH_POS)) /**< BTLELDOCTRL_RF_DISCH Mask */

#define MXC_F_GCR_BTLELDOCTRL_RF_EN_DLY_POS 13 /**< BTLELDOCTRL_RF_EN_DLY Position */
#define MXC_F_GCR_BTLELDOCTRL_RF_EN_DLY_POS 12 /**< BTLELDOCTRL_RF_EN_DLY Position */
#define MXC_F_GCR_BTLELDOCTRL_RF_EN_DLY ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_RF_EN_DLY_POS)) /**< BTLELDOCTRL_RF_EN_DLY Mask */

#define MXC_F_GCR_BTLELDOCTRL_RF_BP_EN_DLY_POS 14 /**< BTLELDOCTRL_RF_BP_EN_DLY Position */
#define MXC_F_GCR_BTLELDOCTRL_RF_BP_EN_DLY ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_RF_BP_EN_DLY_POS)) /**< BTLELDOCTRL_RF_BP_EN_DLY Mask */
#define MXC_F_GCR_BTLELDOCTRL_BB_EN_DLY_POS 13 /**< BTLELDOCTRL_BB_EN_DLY Position */
#define MXC_F_GCR_BTLELDOCTRL_BB_EN_DLY ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_BB_EN_DLY_POS)) /**< BTLELDOCTRL_BB_EN_DLY Mask */

#define MXC_F_GCR_BTLELDOCTRL_BB_BP_EN_DLY_POS 15 /**< BTLELDOCTRL_BB_BP_EN_DLY Position */
#define MXC_F_GCR_BTLELDOCTRL_BB_BP_EN_DLY_POS 14 /**< BTLELDOCTRL_BB_BP_EN_DLY Position */
#define MXC_F_GCR_BTLELDOCTRL_BB_BP_EN_DLY ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_BB_BP_EN_DLY_POS)) /**< BTLELDOCTRL_BB_BP_EN_DLY Mask */

#define MXC_F_GCR_BTLELDOCTRL_RF_BP_EN_DLY_POS 15 /**< BTLELDOCTRL_RF_BP_EN_DLY Position */
#define MXC_F_GCR_BTLELDOCTRL_RF_BP_EN_DLY ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_RF_BP_EN_DLY_POS)) /**< BTLELDOCTRL_RF_BP_EN_DLY Mask */

/**@} end of group GCR_BTLELDOCTRL_Register */

/**
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49 changes: 34 additions & 15 deletions MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/gpio_regs.h
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Original file line number Diff line number Diff line change
Expand Up @@ -96,8 +96,8 @@ typedef struct {
__IO uint32_t wken_clr; /**< <tt>\b 0x54:</tt> GPIO WKEN_CLR Register */
__R uint32_t rsv_0x58;
__IO uint32_t dualedge; /**< <tt>\b 0x5C:</tt> GPIO DUALEDGE Register */
__IO uint32_t padctrl; /**< <tt>\b 0x60:</tt> GPIO PADCTRL Register */
__R uint32_t rsv_0x64;
__IO uint32_t padctrl0; /**< <tt>\b 0x60:</tt> GPIO PADCTRL0 Register */
__IO uint32_t padctrl1; /**< <tt>\b 0x64:</tt> GPIO PADCTRL1 Register */
__IO uint32_t en1; /**< <tt>\b 0x68:</tt> GPIO EN1 Register */
__IO uint32_t en1_set; /**< <tt>\b 0x6C:</tt> GPIO EN1_SET Register */
__IO uint32_t en1_clr; /**< <tt>\b 0x70:</tt> GPIO EN1_CLR Register */
Expand Down Expand Up @@ -143,7 +143,8 @@ typedef struct {
#define MXC_R_GPIO_WKEN_SET ((uint32_t)0x00000050UL) /**< Offset from GPIO Base Address: <tt> 0x0050</tt> */
#define MXC_R_GPIO_WKEN_CLR ((uint32_t)0x00000054UL) /**< Offset from GPIO Base Address: <tt> 0x0054</tt> */
#define MXC_R_GPIO_DUALEDGE ((uint32_t)0x0000005CUL) /**< Offset from GPIO Base Address: <tt> 0x005C</tt> */
#define MXC_R_GPIO_PADCTRL ((uint32_t)0x00000060UL) /**< Offset from GPIO Base Address: <tt> 0x0060</tt> */
#define MXC_R_GPIO_PADCTRL0 ((uint32_t)0x00000060UL) /**< Offset from GPIO Base Address: <tt> 0x0060</tt> */
#define MXC_R_GPIO_PADCTRL1 ((uint32_t)0x00000064UL) /**< Offset from GPIO Base Address: <tt> 0x0064</tt> */
#define MXC_R_GPIO_EN1 ((uint32_t)0x00000068UL) /**< Offset from GPIO Base Address: <tt> 0x0068</tt> */
#define MXC_R_GPIO_EN1_SET ((uint32_t)0x0000006CUL) /**< Offset from GPIO Base Address: <tt> 0x006C</tt> */
#define MXC_R_GPIO_EN1_CLR ((uint32_t)0x00000070UL) /**< Offset from GPIO Base Address: <tt> 0x0070</tt> */
Expand Down Expand Up @@ -472,21 +473,39 @@ typedef struct {

/**
* @ingroup gpio_registers
* @defgroup GPIO_PADCTRL GPIO_PADCTRL
* @brief GPIO Pad Control. Each bit in this register configures the pad for the
* associated GPIO pin in this port.
* @defgroup GPIO_PADCTRL0 GPIO_PADCTRL0
* @brief GPIO Input Mode Config 0. Each bit in this register enables the weak pull-up for
* the associated GPIO pin in this port.
* @{
*/
#define MXC_F_GPIO_PADCTRL_ALL_POS 0 /**< PADCTRL_ALL Position */
#define MXC_F_GPIO_PADCTRL_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_PADCTRL_ALL_POS)) /**< PADCTRL_ALL Mask */
#define MXC_V_GPIO_PADCTRL_ALL_IMPEDANCE ((uint32_t)0x0UL) /**< PADCTRL_ALL_IMPEDANCE Value */
#define MXC_S_GPIO_PADCTRL_ALL_IMPEDANCE (MXC_V_GPIO_PADCTRL_ALL_IMPEDANCE << MXC_F_GPIO_PADCTRL_ALL_POS) /**< PADCTRL_ALL_IMPEDANCE Setting */
#define MXC_V_GPIO_PADCTRL_ALL_PU ((uint32_t)0x1UL) /**< PADCTRL_ALL_PU Value */
#define MXC_S_GPIO_PADCTRL_ALL_PU (MXC_V_GPIO_PADCTRL_ALL_PU << MXC_F_GPIO_PADCTRL_ALL_POS) /**< PADCTRL_ALL_PU Setting */
#define MXC_V_GPIO_PADCTRL_ALL_PD ((uint32_t)0x2UL) /**< PADCTRL_ALL_PD Value */
#define MXC_S_GPIO_PADCTRL_ALL_PD (MXC_V_GPIO_PADCTRL_ALL_PD << MXC_F_GPIO_PADCTRL_ALL_POS) /**< PADCTRL_ALL_PD Setting */
#define MXC_F_GPIO_PADCTRL0_ALL_POS 0 /**< PADCTRL0_ALL Position */
#define MXC_F_GPIO_PADCTRL0_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_PADCTRL0_ALL_POS)) /**< PADCTRL0_ALL Mask */
#define MXC_V_GPIO_PADCTRL0_ALL_IMPEDANCE ((uint32_t)0x0UL) /**< PADCTRL0_ALL_IMPEDANCE Value */
#define MXC_S_GPIO_PADCTRL0_ALL_IMPEDANCE (MXC_V_GPIO_PADCTRL0_ALL_IMPEDANCE << MXC_F_GPIO_PADCTRL0_ALL_POS) /**< PADCTRL0_ALL_IMPEDANCE Setting */
#define MXC_V_GPIO_PADCTRL0_ALL_PU ((uint32_t)0x1UL) /**< PADCTRL0_ALL_PU Value */
#define MXC_S_GPIO_PADCTRL0_ALL_PU (MXC_V_GPIO_PADCTRL0_ALL_PU << MXC_F_GPIO_PADCTRL0_ALL_POS) /**< PADCTRL0_ALL_PU Setting */
#define MXC_V_GPIO_PADCTRL0_ALL_PD ((uint32_t)0x2UL) /**< PADCTRL0_ALL_PD Value */
#define MXC_S_GPIO_PADCTRL0_ALL_PD (MXC_V_GPIO_PADCTRL0_ALL_PD << MXC_F_GPIO_PADCTRL0_ALL_POS) /**< PADCTRL0_ALL_PD Setting */

/**@} end of group GPIO_PADCTRL_Register */
/**@} end of group GPIO_PADCTRL0_Register */

/**
* @ingroup gpio_registers
* @defgroup GPIO_PADCTRL1 GPIO_PADCTRL1
* @brief GPIO Input Mode Config 1. Each bit in this register enables the weak pull-up for
* the associated GPIO pin in this port.
* @{
*/
#define MXC_F_GPIO_PADCTRL1_ALL_POS 0 /**< PADCTRL1_ALL Position */
#define MXC_F_GPIO_PADCTRL1_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_PADCTRL1_ALL_POS)) /**< PADCTRL1_ALL Mask */
#define MXC_V_GPIO_PADCTRL1_ALL_IMPEDANCE ((uint32_t)0x0UL) /**< PADCTRL1_ALL_IMPEDANCE Value */
#define MXC_S_GPIO_PADCTRL1_ALL_IMPEDANCE (MXC_V_GPIO_PADCTRL1_ALL_IMPEDANCE << MXC_F_GPIO_PADCTRL1_ALL_POS) /**< PADCTRL1_ALL_IMPEDANCE Setting */
#define MXC_V_GPIO_PADCTRL1_ALL_PU ((uint32_t)0x1UL) /**< PADCTRL1_ALL_PU Value */
#define MXC_S_GPIO_PADCTRL1_ALL_PU (MXC_V_GPIO_PADCTRL1_ALL_PU << MXC_F_GPIO_PADCTRL1_ALL_POS) /**< PADCTRL1_ALL_PU Setting */
#define MXC_V_GPIO_PADCTRL1_ALL_PD ((uint32_t)0x2UL) /**< PADCTRL1_ALL_PD Value */
#define MXC_S_GPIO_PADCTRL1_ALL_PD (MXC_V_GPIO_PADCTRL1_ALL_PD << MXC_F_GPIO_PADCTRL1_ALL_POS) /**< PADCTRL1_ALL_PD Setting */

/**@} end of group GPIO_PADCTRL1_Register */

/**
* @ingroup gpio_registers
Expand Down
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