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Adding ad353xr project for coraz7s Signed-off-by: Alexis Czezar Torreno <[email protected]>
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| #################################################################################### | ||
| ## Copyright (c) 2018 - 2023 Analog Devices, Inc. | ||
| ### SPDX short identifier: BSD-1-Clause | ||
| ## Auto-generated, do not modify! | ||
| #################################################################################### | ||
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| include ../scripts/project-toplevel.mk |
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| # AD353XR HDL Driver | ||
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| Here are some pointers to help you: | ||
| * [Board Product Page] To Be Released | ||
| * Parts : [ AD353XR Family of Low Power, Buffered Voltage Output, SPI DAC ] To Be Released | ||
| * Project Doc: https://wiki.analog.com/resources/eval/user-guides/ad353xr | ||
| * HDL Doc: https://wiki.analog.com/resources/eval/user-guides/ad353xr | ||
| * Linux Drivers: To be added after PR and Upstream |
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| #################################################################################### | ||
| ## Copyright (c) 2018 - 2023 Analog Devices, Inc. | ||
| ### SPDX short identifier: BSD-1-Clause | ||
| ## Auto-generated, do not modify! | ||
| #################################################################################### | ||
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| PROJECT_NAME := ad353xR_coraz7s | ||
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| M_DEPS += ../../scripts/adi_pd.tcl | ||
| M_DEPS += ../../common/coraz7s/coraz7s_system_ps7.tcl | ||
| M_DEPS += ../../common/coraz7s/coraz7s_system_constr.xdc | ||
| M_DEPS += ../../common/coraz7s/coraz7s_system_bd.tcl | ||
| M_DEPS += ../../../library/common/ad_iobuf.v | ||
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| LIB_DEPS += axi_sysid | ||
| LIB_DEPS += sysid_rom | ||
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| include ../../scripts/project-xilinx.mk |
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| ############################################################################### | ||
| ## Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved. | ||
| ### SPDX short identifier: ADIBSD | ||
| ############################################################################### | ||
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| source $ad_hdl_dir/projects/common/coraz7s/coraz7s_system_bd.tcl | ||
| source $ad_hdl_dir/projects/scripts/adi_pd.tcl | ||
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| #system ID | ||
| ad_ip_parameter axi_sysid_0 CONFIG.ROM_ADDR_BITS 9 | ||
| ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "[pwd]/mem_init_sys.txt" | ||
| ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9 | ||
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| sysid_gen_sys_init_file | ||
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| set sys_dma_clk [get_bd_nets sys_dma_clk] |
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| ############################################################################### | ||
| ## Copyright (C) 2022-2024 Analog Devices, Inc. All rights reserved. | ||
| ### SPDX short identifier: ADIBSD | ||
| ############################################################################### | ||
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| # DAC SPI interface | ||
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| set_property -dict {PACKAGE_PIN H15 IOSTANDARD LVCMOS33} [get_ports spi_sck] ; ## ck_sck H15 | ||
| set_property -dict {PACKAGE_PIN T12 IOSTANDARD LVCMOS33} [get_ports spi_sdo] ; ## ck_mosi T12 | ||
| set_property -dict {PACKAGE_PIN W15 IOSTANDARD LVCMOS33} [get_ports spi_sdi] ; ## ck_miso W15 | ||
| set_property -dict {PACKAGE_PIN F16 IOSTANDARD LVCMOS33} [get_ports spi_csb] ; ## ck_ss F16 | ||
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| # DAC GPIO interface | ||
| set_property -dict {PACKAGE_PIN V13 IOSTANDARD LVCMOS33} [get_ports dac_resetb] ; ## ck_io[1] V13 | ||
| set_property -dict {PACKAGE_PIN T14 IOSTANDARD LVCMOS33} [get_ports dac_ldacb] ; ## ck_io[2] T14 |
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| ############################################################################### | ||
| ## Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved. | ||
| ### SPDX short identifier: ADIBSD | ||
| ############################################################################### | ||
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| source ../../../scripts/adi_env.tcl | ||
| source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl | ||
| source $ad_hdl_dir/projects/scripts/adi_board.tcl | ||
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| adi_project ad353xR_coraz7s | ||
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| adi_project_files ad353xR_coraz7s [list \ | ||
| "$ad_hdl_dir/library/common/ad_iobuf.v" \ | ||
| "system_top.v" \ | ||
| "system_constr.xdc" \ | ||
| "$ad_hdl_dir/projects/common/coraz7s/coraz7s_system_constr.xdc"] | ||
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| set_property PROCESSING_ORDER LATE [get_files system_constr.xdc] | ||
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| adi_project_run ad353xR_coraz7s |
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| // *************************************************************************** | ||
| // *************************************************************************** | ||
| // Copyright (C) 2022-2024 Analog Devices, Inc. All rights reserved. | ||
| // | ||
| // In this HDL repository, there are many different and unique modules, consisting | ||
| // of various HDL (Verilog or VHDL) components. The individual modules are | ||
| // developed independently, and may be accompanied by separate and unique license | ||
| // terms. | ||
| // | ||
| // The user should read each of these license terms, and understand the | ||
| // freedoms and responsibilities that he or she has by using this source/core. | ||
| // | ||
| // This core is distributed in the hope that it will be useful, but WITHOUT ANY | ||
| // WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR | ||
| // A PARTICULAR PURPOSE. | ||
| // | ||
| // Redistribution and use of source or resulting binaries, with or without modification | ||
| // of this file, are permitted under one of the following two license terms: | ||
| // | ||
| // 1. The GNU General Public License version 2 as published by the | ||
| // Free Software Foundation, which can be found in the top level directory | ||
| // of this repository (LICENSE_GPL2), and also online at: | ||
| // <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html> | ||
| // | ||
| // OR | ||
| // | ||
| // 2. An ADI specific BSD license, which can be found in the top level directory | ||
| // of this repository (LICENSE_ADIBSD), and also on-line at: | ||
| // https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD | ||
| // This will allow to generate bit files and not release the source code, | ||
| // as long as it attaches to an ADI device. | ||
| // | ||
| // *************************************************************************** | ||
| // *************************************************************************** | ||
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| `timescale 1ns/100ps | ||
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| module system_top ( | ||
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| inout [14:0] ddr_addr, | ||
| inout [ 2:0] ddr_ba, | ||
| inout ddr_cas_n, | ||
| inout ddr_ck_n, | ||
| inout ddr_ck_p, | ||
| inout ddr_cke, | ||
| inout ddr_cs_n, | ||
| inout [ 3:0] ddr_dm, | ||
| inout [31:0] ddr_dq, | ||
| inout [ 3:0] ddr_dqs_n, | ||
| inout [ 3:0] ddr_dqs_p, | ||
| inout ddr_odt, | ||
| inout ddr_ras_n, | ||
| inout ddr_reset_n, | ||
| inout ddr_we_n, | ||
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| inout fixed_io_ddr_vrn, | ||
| inout fixed_io_ddr_vrp, | ||
| inout [53:0] fixed_io_mio, | ||
| inout fixed_io_ps_clk, | ||
| inout fixed_io_ps_porb, | ||
| inout fixed_io_ps_srstb, | ||
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| inout [ 1:0] btn, | ||
| inout [ 5:0] led, | ||
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| inout iic_ard_scl, | ||
| inout iic_ard_sda, | ||
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| output dac_resetb, | ||
| output dac_ldacb, | ||
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| input spi_sdi, | ||
| output spi_sdo, | ||
| output spi_sck, | ||
| output spi_csb | ||
| ); | ||
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| // internal signals | ||
| wire [63:0] gpio_i; | ||
| wire [63:0] gpio_o; | ||
| wire [63:0] gpio_t; | ||
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| // assignments | ||
| assign gpio_i[63:32] = gpio_o[63:32]; | ||
| assign gpio_i[31:8] = gpio_o[31:8]; | ||
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| assign dac_resetb = gpio_o[33]; | ||
| assign dac_ldacb = gpio_o[34]; | ||
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| // instantiations | ||
| ad_iobuf #( | ||
| .DATA_WIDTH (2) | ||
| ) i_iobuf_buttons ( | ||
| .dio_t (gpio_t[1:0]), | ||
| .dio_i (gpio_o[1:0]), | ||
| .dio_o (gpio_i[1:0]), | ||
| .dio_p (btn)); | ||
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| ad_iobuf #( | ||
| .DATA_WIDTH (6) | ||
| ) i_iobuf_leds ( | ||
| .dio_t (gpio_t[7:2]), | ||
| .dio_i (gpio_o[7:2]), | ||
| .dio_o (gpio_i[7:2]), | ||
| .dio_p (led)); | ||
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| system_wrapper i_system_wrapper ( | ||
| .ddr_addr (ddr_addr), | ||
| .ddr_ba (ddr_ba), | ||
| .ddr_cas_n (ddr_cas_n), | ||
| .ddr_ck_n (ddr_ck_n), | ||
| .ddr_ck_p (ddr_ck_p), | ||
| .ddr_cke (ddr_cke), | ||
| .ddr_cs_n (ddr_cs_n), | ||
| .ddr_dm (ddr_dm), | ||
| .ddr_dq (ddr_dq), | ||
| .ddr_dqs_n (ddr_dqs_n), | ||
| .ddr_dqs_p (ddr_dqs_p), | ||
| .ddr_odt (ddr_odt), | ||
| .ddr_ras_n (ddr_ras_n), | ||
| .ddr_reset_n (ddr_reset_n), | ||
| .ddr_we_n (ddr_we_n), | ||
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| .fixed_io_ddr_vrn (fixed_io_ddr_vrn), | ||
| .fixed_io_ddr_vrp (fixed_io_ddr_vrp), | ||
| .fixed_io_mio (fixed_io_mio), | ||
| .fixed_io_ps_clk (fixed_io_ps_clk), | ||
| .fixed_io_ps_porb (fixed_io_ps_porb), | ||
| .fixed_io_ps_srstb (fixed_io_ps_srstb), | ||
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| .gpio_i (gpio_i), | ||
| .gpio_o (gpio_o), | ||
| .gpio_t (gpio_t), | ||
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| .spi0_clk_i (1'b0), | ||
| .spi0_clk_o (spi_sck), | ||
| .spi0_csn_0_o (spi_csb), | ||
| .spi0_csn_1_o (), | ||
| .spi0_csn_2_o (), | ||
| .spi0_csn_i (1'b1), | ||
| .spi0_sdi_i (spi_sdi), | ||
| .spi0_sdo_i (1'b0), | ||
| .spi0_sdo_o (spi_sdo), | ||
| .spi1_clk_i (1'b0), | ||
| .spi1_clk_o (), | ||
| .spi1_csn_0_o (), | ||
| .spi1_csn_1_o (), | ||
| .spi1_csn_2_o (), | ||
| .spi1_csn_i (1'b1), | ||
| .spi1_sdi_i (1'b0), | ||
| .spi1_sdo_i (1'b0), | ||
| .spi1_sdo_o(), | ||
| .iic_ard_scl_io (iic_ard_scl), | ||
| .iic_ard_sda_io (iic_ard_sda)); | ||
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| endmodule |