projects: ad7616: Project development

Signed-off-by: Pop Ioan Daniel <[email protected]>
analogdevicesinc · Nov 28, 2024 · 458a921 · 458a921
1 parent 357b58d
commit 458a921
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Showing 7 changed files with 48 additions and 63 deletions.
diff --git a/projects/ad7616_sdz/Makefile b/projects/ad7616_sdz/Makefile
@@ -1,5 +1,5 @@
 ####################################################################################
-## Copyright (c) 2018 - 2023 Analog Devices, Inc.
+## Copyright (c) 2018 - 2024 Analog Devices, Inc.
 ### SPDX short identifier: BSD-1-Clause
 ## Auto-generated, do not modify!
 ####################################################################################

diff --git a/projects/ad7616_sdz/common/ad7616_bd.tcl b/projects/ad7616_sdz/common/ad7616_bd.tcl
@@ -4,31 +4,10 @@
 ###############################################################################
 ##--------------------------------------------------------------
 
-# IMPORTANT: Set AD7616 operation and interface mode
-#
-# The get_env_param procedure retrieves parameter value from the environment if exists,
-# other case returns the default value specified in its second parameter field.
-#
-#   How to use over-writable parameters from the environment:
-#
-#    e.g.
-#      make SER_PAR_N=0
-#
-#    SER_PAR_N  - Defines the interface type (serial OR parallel)
-#               - Default value is 1
-#
-# LEGEND: Serial    - 1
-#         Parallel  - 0
-#
-# NOTE : This switch is a 'hardware' switch. Please rebuild the design if the
-# variable has been changed.
-#     SL5 - mounted - Serial
-#     SL5 - unmounted - Parallel
-#
-##--------------------------------------------------------------
+# system level parameter
 
-set SER_PAR_N $ad_project_params(SER_PAR_N)
-puts "build parameters: SER_PAR_N: $SER_PAR_N"
+set INTF $ad_project_params(INTF)
+puts "build parameters: INTF: $INTF"
 
 # control lines
 
@@ -50,28 +29,21 @@ ad_ip_parameter axi_ad7616_dma CONFIG.DMA_DATA_WIDTH_DEST 64
 ad_ip_instance axi_pwm_gen ad7616_pwm_gen
 ad_ip_parameter ad7616_pwm_gen CONFIG.PULSE_0_PERIOD 100
 ad_ip_parameter ad7616_pwm_gen CONFIG.PULSE_0_WIDTH 5
-ad_ip_parameter ad7616_pwm_gen CONFIG.ASYNC_CLK_EN 1
-
-# axi_clkgen
-
-ad_ip_instance axi_clkgen spi_clkgen
-ad_ip_parameter spi_clkgen CONFIG.CLK0_DIV 6
-ad_ip_parameter spi_clkgen CONFIG.VCO_DIV 1
-ad_ip_parameter spi_clkgen CONFIG.VCO_MUL 6
+ad_ip_parameter ad7616_pwm_gen CONFIG.ASYNC_CLK_EN 0
 
 # trigger to BUSY's negative edge
 
 create_bd_cell -type module -reference sync_bits busy_sync
 create_bd_cell -type module -reference ad_edge_detect busy_capture
 set_property -dict [list CONFIG.EDGE 1] [get_bd_cells busy_capture]
 
-ad_connect spi_clk busy_capture/clk
+ad_connect $sys_cpu_clk busy_capture/clk
 ad_connect busy_capture/rst GND
-ad_connect spi_clk busy_sync/out_clk
+ad_connect $sys_cpu_clk busy_sync/out_clk
 ad_connect busy_sync/in_bits rx_busy
 ad_connect busy_sync/out_bits busy_capture/signal_in
 
-if {$SER_PAR_N == 1} {
+if {$INTF == 1} {
   create_bd_intf_port -mode Master -vlnv analog.com:interface:spi_engine_rtl:1.0 ad7616_spi
 
   source $ad_hdl_dir/library/spi_engine/scripts/spi_engine.tcl
@@ -94,16 +66,20 @@ if {$SER_PAR_N == 1} {
   # interface connections
 
   ad_connect  $sys_cpu_clk $hier_spi_engine/clk
-  ad_connect  spi_clk $hier_spi_engine/spi_clk
+  ad_connect  $sys_cpu_clk $hier_spi_engine/spi_clk
+
   ad_connect  sys_cpu_resetn $hier_spi_engine/resetn
   ad_connect  $hier_spi_engine/m_spi ad7616_spi
 
-  ad_connect  spi_clk axi_ad7616_dma/s_axis_aclk
+  ad_connect  $sys_cpu_clk axi_ad7616_dma/s_axis_aclk
   ad_connect  axi_ad7616_dma/s_axis $hier_spi_engine/m_axis_sample
 
   ad_connect  busy_sync/out_resetn $hier_spi_engine/${hier_spi_engine}_axi_regmap/spi_resetn
   ad_connect  busy_capture/signal_out $hier_spi_engine/${hier_spi_engine}_offload/trigger
 
+  ad_ip_parameter ad7616_pwm_gen CONFIG.ASYNC_CLK_EN 1
+  ad_connect $sys_cpu_clk ad7616_pwm_gen/ext_clk
+
   # interconnect
 
   ad_cpu_interconnect  0x44A00000 $hier_spi_engine/${hier_spi_engine}_axi_regmap
@@ -122,12 +98,18 @@ if {$SER_PAR_N == 1} {
   create_bd_port -dir O rx_wr_n
   create_bd_port -dir O rx_cs_n
 
-  ad_ip_parameter axi_ad7616_dma CONFIG.DMA_DATA_WIDTH_SRC 16
+  ad_ip_parameter axi_ad7616_dma CONFIG.DMA_DATA_WIDTH_SRC 256
   ad_ip_parameter axi_ad7616_dma CONFIG.DMA_TYPE_SRC 2
   ad_ip_parameter axi_ad7616_dma CONFIG.SYNC_TRANSFER_START 1
 
   ad_ip_instance axi_ad7616 axi_ad7616
 
+  # cpack
+
+  ad_ip_instance util_cpack2 ad7616_adc_pack
+  ad_ip_parameter ad7616_adc_pack CONFIG.NUM_OF_CHANNELS 16
+  ad_ip_parameter ad7616_adc_pack CONFIG.SAMPLE_DATA_WIDTH 16;
+
   # interface connections
 
   ad_connect  rx_db_o axi_ad7616/rx_db_o
@@ -137,10 +119,20 @@ if {$SER_PAR_N == 1} {
   ad_connect  rx_wr_n axi_ad7616/rx_wr_n
   ad_connect  rx_cs_n axi_ad7616/rx_cs_n
 
-  ad_connect  $sys_cpu_clk axi_ad7616_dma/fifo_wr_clk
-  ad_connect  axi_ad7616/adc_valid axi_ad7616_dma/fifo_wr_en
-  ad_connect  axi_ad7616/adc_data axi_ad7616_dma/fifo_wr_din
-  ad_connect  axi_ad7616/adc_sync axi_ad7616_dma/sync
+  ad_connect  axi_ad7616/adc_clk axi_ad7616_dma/fifo_wr_clk
+
+  ad_connect  axi_ad7616/adc_clk ad7616_adc_pack/clk
+  ad_connect  axi_ad7616/adc_reset ad7616_adc_pack/reset
+  ad_connect  axi_ad7616/adc_valid ad7616_adc_pack/fifo_wr_en
+
+  ad_connect ad7616_adc_pack/packed_fifo_wr axi_ad7616_dma/fifo_wr
+  ad_connect ad7616_adc_pack/packed_sync axi_ad7616_dma/sync
+  ad_connect ad7616_adc_pack/fifo_wr_overflow axi_ad7616/adc_dovf
+
+  for {set i 0} {$i < 16} {incr i} {
+    ad_connect axi_ad7616/adc_data_$i ad7616_adc_pack/fifo_wr_data_$i
+    ad_connect axi_ad7616/adc_enable_$i ad7616_adc_pack/enable_$i
+  }
 
   ad_connect busy_capture/signal_out axi_ad7616/rx_trigger
   ad_connect busy_sync/out_resetn sys_cpu_resetn
@@ -152,20 +144,16 @@ if {$SER_PAR_N == 1} {
 }
 
 # interface connections
-ad_connect  $sys_cpu_clk spi_clkgen/clk
-ad_connect  spi_clk spi_clkgen/clk_0
-
+
 ad_connect  ad7616_pwm_gen/pwm_0 rx_cnvst
 ad_connect  $sys_cpu_clk ad7616_pwm_gen/s_axi_aclk
 ad_connect  sys_cpu_resetn ad7616_pwm_gen/s_axi_aresetn
-ad_connect  spi_clk ad7616_pwm_gen/ext_clk
 ad_connect  $sys_cpu_clk axi_ad7616_dma/s_axi_aclk
 ad_connect  sys_cpu_resetn axi_ad7616_dma/m_dest_axi_aresetn
 
 # interconnect
 
 ad_cpu_interconnect  0x44A30000 axi_ad7616_dma
-ad_cpu_interconnect  0x44A70000 spi_clkgen
 ad_cpu_interconnect  0x44B00000 ad7616_pwm_gen
 
 # memory interconnect

diff --git a/projects/ad7616_sdz/common/ad7616_serial_fmc.txt b/projects/ad7616_sdz/common/ad7616_serial_fmc.txt
@@ -12,7 +12,7 @@ M22     FMC_LPC_LA04_N       CSn              ad7616_spi_cs     LVCOMOS25     #N
 A18     FMC_LPC_LA24_P       CONVST           adc_cnvst         LVCOMOS25     #N/A
 E20     FMC_LPC_LA21_N       CHSEL0           adc_chsel[0]      LVCOMOS25     #N/A
 E18     FMC_LPC_LA26_N       CHSEL1           adc_chsel[1]      LVCOMOS25     #N/A
-D22     FMC_LPC_LA25_P       CHSEL2           adc_chsel[2       LVCOMOS25     #N/A
+D22     FMC_LPC_LA25_P       CHSEL2           adc_chsel[2]      LVCOMOS25     #N/A
 E19     FMC_LPC_LA21_P       HW_RNGSEL0       adc_hw_rngsel[0]  LVCOMOS25     #N/A
 F18     FMC_LPC_LA26_P       HW_RNGSEL1       adc_hw_rngsel[1]  LVCOMOS25     #N/A
 T19     FMC_LPC_LA10_N       BUSY             adc_busy          LVCOMOS25     #N/A

diff --git a/projects/ad7616_sdz/zed/Makefile b/projects/ad7616_sdz/zed/Makefile
@@ -1,5 +1,5 @@
 ####################################################################################
-## Copyright (c) 2018 - 2023 Analog Devices, Inc.
+## Copyright (c) 2018 - 2024 Analog Devices, Inc.
 ### SPDX short identifier: BSD-1-Clause
 ## Auto-generated, do not modify!
 ####################################################################################
@@ -31,5 +31,6 @@ LIB_DEPS += spi_engine/spi_engine_interconnect
 LIB_DEPS += spi_engine/spi_engine_offload
 LIB_DEPS += sysid_rom
 LIB_DEPS += util_i2c_mixer
+LIB_DEPS += util_pack/util_cpack2
 
 include ../../scripts/project-xilinx.mk
diff --git a/projects/ad7616_sdz/zed/system_bd.tcl b/projects/ad7616_sdz/zed/system_bd.tcl
@@ -19,6 +19,6 @@ ad_ip_parameter axi_sysid_0 CONFIG.ROM_ADDR_BITS 9
 ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "$mem_init_sys_file_path/mem_init_sys.txt"
 ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9
 
-set sys_cstring "SER_PAR_N=$ad_project_params(SER_PAR_N)"
+set sys_cstring "INTF=$ad_project_params(INTF)"
 
 sysid_gen_sys_init_file $sys_cstring
diff --git a/projects/ad7616_sdz/zed/system_project.tcl b/projects/ad7616_sdz/zed/system_project.tcl
@@ -1,5 +1,5 @@
 ###############################################################################
-## Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved.
+## Copyright (C) 2019-2024 Analog Devices, Inc. All rights reserved.
 ### SPDX short identifier: ADIBSD
 ###############################################################################
 
@@ -16,9 +16,9 @@ source $ad_hdl_dir/projects/scripts/adi_board.tcl
 #   How to use over-writable parameters from the environment:
 #
 #    e.g.
-#      make SER_PAR_N=0
+#      make INTF=0
 #
-#    SER_PAR_N  - Defines the interface type (serial OR parallel)
+#    INTF  - Defines the interface type (serial OR parallel)
 #               - Default value is 1
 #
 # LEGEND: Serial    - 1
@@ -31,21 +31,17 @@ source $ad_hdl_dir/projects/scripts/adi_board.tcl
 #
 ##--------------------------------------------------------------
 
-if {[info exists ::env(SER_PAR_N)]} {
-  set S_SER_PAR_N [get_env_param SER_PAR_N 0]
-} elseif {![info exists SER_PAR_N]} {
-  set S_SER_PAR_N 1
-}
+set INTF [get_env_param INTF 0]
 
 adi_project ad7616_sdz_zed 0 [list \
-  SER_PAR_N  $S_SER_PAR_N \
+   INTF $INTF \
 ]
 
 adi_project_files ad7616_sdz_zed [list \
   "$ad_hdl_dir/library/common/ad_iobuf.v" \
   "$ad_hdl_dir/projects/common/zed/zed_system_constr.xdc"]
 
-switch $S_SER_PAR_N {
+switch $INTF {
   1 {
     adi_project_files ad7616_sdz_zed [list \
       "system_top_si.v" \

diff --git a/projects/ad7616_sdz/zed/system_top_pi.v b/projects/ad7616_sdz/zed/system_top_pi.v
@@ -1,6 +1,6 @@
 // ***************************************************************************
 // ***************************************************************************
-// Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved.
+// Copyright (C) 2019-2024 Analog Devices, Inc. All rights reserved.
 //
 // In this HDL repository, there are many different and unique modules, consisting
 // of various HDL (Verilog or VHDL) components. The individual modules are
@@ -135,7 +135,7 @@ module system_top (
   ad_iobuf #(
     .DATA_WIDTH(16)
   ) i_iobuf_adc_db (
-    .dio_t(adc_db_t),
+    .dio_t({16{adc_db_t}}),
     .dio_i(adc_db_o[15:0]),
     .dio_o(adc_db_i[15:0]),
     .dio_p(adc_db[15:0]));