V10: Reorder Framelock register

Signed-off-by: Jorge Marques <[email protected]>
analogdevicesinc · Oct 24, 2024 · d105e07 · d105e07
1 parent 65a8923
commit d105e07
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Showing 2 changed files with 18 additions and 18 deletions.
diff --git a/docs/regmap/adi_regmap_dmac.txt b/docs/regmap/adi_regmap_dmac.txt
@@ -677,7 +677,16 @@ If ``AUTORUN`` is set, the default value of the field is ``AUTORUN_FRAMELOCK_CON
 ENDFIELD
 
 FIELD
-[9] 0x0
+[15:8] 0x00
+FRAMENUM
+RW
+The total number of video frame buffers.
+Related to MAX_NUM_FRAMES synthesis parameter.
+If ``AUTORUN`` is set, the default value of the field is ``AUTORUN_FRAMELOCK_CONFIG[7:0]``.
+ENDFIELD
+
+FIELD
+[1] 0x0
 WAIT_WRITER
 RW
 If WAIT_WRITER is unset, enable the generation of new request right away.
@@ -688,23 +697,14 @@ If ``AUTORUN`` is set, the default value of the field is ``AUTORUN_FRAMELOCK_CON
 ENDFIELD
 
 FIELD
-[8] 0x0
+[0] 0x0
 MODE
 RW
 Select operating mode of the framebuffer.
 (0 - Frame rate conversion mode (dynamic), 1 - Output delay mode (simple))
 If ``AUTORUN`` is set, the default value of the field is ``AUTORUN_FRAMELOCK_CONFIG[8]``.
 ENDFIELD
 
-FIELD
-[7:0] 0x00
-FRAMENUM
-RW
-The total number of video frame buffers.
-Related to MAX_NUM_FRAMES synthesis parameter.
-If ``AUTORUN`` is set, the default value of the field is ``AUTORUN_FRAMELOCK_CONFIG[7:0]``.
-ENDFIELD
-
 ############################################################################################
 ############################################################################################
 

diff --git a/library/axi_dmac/axi_dmac_regmap_request.v b/library/axi_dmac/axi_dmac_regmap_request.v
@@ -225,10 +225,10 @@ module axi_dmac_regmap_request #(
     9'h115: up_rdata <= response_sg_desc_id;
     9'h116: begin
               up_rdata <= 'h0;
-              up_rdata[MAX_NUM_FRAMES_WIDTH:0] <= request_flock_framenum;
-              up_rdata[8] <= request_flock_mode;
-              up_rdata[9] <= request_flock_wait_writer;
               up_rdata[16 +:(MAX_NUM_FRAMES_WIDTH+1)] <= request_flock_distance;
+              up_rdata[8 +:(MAX_NUM_FRAMES_WIDTH+1)] <= request_flock_framenum;
+              up_rdata[1] <= request_flock_wait_writer;
+              up_rdata[0] <= request_flock_mode;
             end
     9'h117: up_rdata <= request_flock_stride;
     9'h11f: up_rdata <= {request_sg_address[ADDR_LOW_MSB:BYTES_PER_BEAT_WIDTH_SG],{BYTES_PER_BEAT_WIDTH_SG{1'b0}}};
@@ -304,10 +304,10 @@ module axi_dmac_regmap_request #(
       end else if (up_wreq == 1'b1) begin
         case (up_waddr)
           9'h116: begin
-            up_dma_flock_framenum <= up_wdata[MAX_NUM_FRAMES_WIDTH:0];
-            up_dma_flock_mode <= up_wdata[8];
-            up_dma_flock_wait_writer <= up_wdata[9];
-            up_dma_flock_distance <= up_wdata[16 +: (MAX_NUM_FRAMES_WIDTH+1)];
+            up_dma_flock_distance <= up_wdata[16 +:(MAX_NUM_FRAMES_WIDTH+1)];
+            up_dma_flock_framenum <= up_wdata[8 +:(MAX_NUM_FRAMES_WIDTH+1)];
+            up_dma_flock_wait_writer <= up_wdata[1];
+            up_dma_flock_mode <= up_wdata[0];
           end
           9'h117: up_dma_flock_stride <= up_wdata[DMA_AXI_ADDR_WIDTH-1:0];
         endcase