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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,16 @@ | ||
| #################################################################################### | ||
| ## Copyright (c) 2018 - 2023 Analog Devices, Inc. | ||
| ### SPDX short identifier: BSD-1-Clause | ||
| ## Auto-generated, do not modify! | ||
| #################################################################################### | ||
|
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| PROJECT_NAME := ad719x_asdz_de10nano | ||
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| M_DEPS += ../../scripts/adi_pd.tcl | ||
| M_DEPS += ../../common/de10nano/de10nano_system_qsys.tcl | ||
| M_DEPS += ../../common/de10nano/de10nano_system_assign.tcl | ||
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| LIB_DEPS += axi_sysid | ||
| LIB_DEPS += sysid_rom | ||
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| include ../../scripts/project-intel.mk |
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| ############################################################################### | ||
| ## Copyright (C) 2020-2023 Analog Devices, Inc. All rights reserved. | ||
| ### SPDX short identifier: ADIBSD | ||
| ############################################################################### | ||
|
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| # de10-nano | ||
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| create_clock -period "20.000 ns" -name sys_clk [get_ports {sys_clk}] | ||
| create_clock -period "16.666 ns" -name usb1_clk [get_ports {usb1_clk}] | ||
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| derive_pll_clocks | ||
| derive_clock_uncertainty |
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| ############################################################################### | ||
| ## Copyright (C) 2020-2023 Analog Devices, Inc. All rights reserved. | ||
| ### SPDX short identifier: ADIBSD | ||
| ############################################################################### | ||
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| set REQUIRED_QUARTUS_VERSION 22.1std.0 | ||
| set QUARTUS_PRO_ISUSED 0 | ||
| source ../../../scripts/adi_env.tcl | ||
| source ../../scripts/adi_project_intel.tcl | ||
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| adi_project ad719x_asdz_de10nano | ||
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| source $ad_hdl_dir/projects/common/de10nano/de10nano_system_assign.tcl | ||
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| # | ||
| ## down-rade Critical Warning reated to a asynchronous RAM in DMAC | ||
| # | ||
| ## "mixed_port_feed_through_mode" parameter of RAM can not have value "old" | ||
| set_global_assignment -name MESSAGE_DISABLE 15003 | ||
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| # files | ||
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| # SPI interface for ad719x | ||
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| set_location_assignment PIN_AH12 -to ad719x_spi_sclk ; ## Arduino_IO13 | ||
| set_location_assignment PIN_AH11 -to ad719x_spi_miso ; ## Arduino_IO12 | ||
| set_location_assignment PIN_AG16 -to ad719x_spi_mosi ; ## Arduino_IO11 | ||
| set_location_assignment PIN_AF15 -to ad719x_spi_cs_1 ; ## Arduino_IO10 | ||
| set_location_assignment PIN_AE15 -to ad719x_spi_cs_2 ; ## Arduino_IO9 | ||
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| set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ad719x_spi_sclk | ||
| set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ad719x_spi_miso | ||
| set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ad719x_spi_mosi | ||
| set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ad719x_spi_cs_1 | ||
| set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ad719x_spi_cs_2 | ||
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| # I2C | ||
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| set_location_assignment PIN_AG11 -to i2c_scl ; ## Arduino_IO15 | ||
| set_location_assignment PIN_AH9 -to i2c_sda ; ## Arduino_IO14 | ||
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| set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to i2c_scl | ||
| set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to i2c_sda | ||
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| # synchronization and timing | ||
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| set_location_assignment PIN_U14 -to ad719x_sync_n ; ## Arduino_IO4 | ||
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| set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ad719x_sync_n | ||
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| execute_flow -compile |
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| @@ -0,0 +1,14 @@ | ||
| ############################################################################### | ||
| ## Copyright (C) 2020-2023 Analog Devices, Inc. All rights reserved. | ||
| ### SPDX short identifier: ADIBSD | ||
| ############################################################################### | ||
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| source $ad_hdl_dir/projects/scripts/adi_pd.tcl | ||
| source $ad_hdl_dir/projects/common/de10nano/de10nano_system_qsys.tcl | ||
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| #system ID | ||
| set_instance_parameter_value axi_sysid_0 {ROM_ADDR_BITS} {9} | ||
| set_instance_parameter_value rom_sys_0 {PATH_TO_FILE} "$mem_init_sys_file_path/mem_init_sys.txt" | ||
| set_instance_parameter_value rom_sys_0 {ROM_ADDR_BITS} {9} | ||
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| sysid_gen_sys_init_file |
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| // *************************************************************************** | ||
| // *************************************************************************** | ||
| // Copyright (C) 2020-2023 Analog Devices, Inc. All rights reserved. | ||
| // | ||
| // In this HDL repository, there are many different and unique modules, consisting | ||
| // of various HDL (Verilog or VHDL) components. The individual modules are | ||
| // developed independently, and may be accompanied by separate and unique license | ||
| // terms. | ||
| // | ||
| // The user should read each of these license terms, and understand the | ||
| // freedoms and responsibilities that he or she has by using this source/core. | ||
| // | ||
| // This core is distributed in the hope that it will be useful, but WITHOUT ANY | ||
| // WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR | ||
| // A PARTICULAR PURPOSE. | ||
| // | ||
| // Redistribution and use of source or resulting binaries, with or without modification | ||
| // of this file, are permitted under one of the following two license terms: | ||
| // | ||
| // 1. The GNU General Public License version 2 as published by the | ||
| // Free Software Foundation, which can be found in the top level directory | ||
| // of this repository (LICENSE_GPL2), and also online at: | ||
| // <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html> | ||
| // | ||
| // OR | ||
| // | ||
| // 2. An ADI specific BSD license, which can be found in the top level directory | ||
| // of this repository (LICENSE_ADIBSD), and also on-line at: | ||
| // https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD | ||
| // This will allow to generate bit files and not release the source code, | ||
| // as long as it attaches to an ADI device. | ||
| // | ||
| // *************************************************************************** | ||
| // *************************************************************************** | ||
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| `timescale 1ns/100ps | ||
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| module system_top ( | ||
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| // clock and resets | ||
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| input sys_clk, | ||
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| // hps-ddr | ||
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| output [14:0] ddr3_a, | ||
| output [ 2:0] ddr3_ba, | ||
| output ddr3_reset_n, | ||
| output ddr3_ck_p, | ||
| output ddr3_ck_n, | ||
| output ddr3_cke, | ||
| output ddr3_cs_n, | ||
| output ddr3_ras_n, | ||
| output ddr3_cas_n, | ||
| output ddr3_we_n, | ||
| inout [31:0] ddr3_dq, | ||
| inout [ 3:0] ddr3_dqs_p, | ||
| inout [ 3:0] ddr3_dqs_n, | ||
| output [ 3:0] ddr3_dm, | ||
| output ddr3_odt, | ||
| input ddr3_rzq, | ||
|
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| // hps-ethernet | ||
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| output eth1_tx_clk, | ||
| output eth1_tx_ctl, | ||
| output [ 3:0] eth1_tx_d, | ||
| input eth1_rx_clk, | ||
| input eth1_rx_ctl, | ||
| input [ 3:0] eth1_rx_d, | ||
| output eth1_mdc, | ||
| inout eth1_mdio, | ||
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| // hps-sdio | ||
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| output sdio_clk, | ||
| inout sdio_cmd, | ||
| inout [ 3:0] sdio_d, | ||
|
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| // hps-spim1 | ||
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| output spim1_ss0, | ||
| output spim1_clk, | ||
| output spim1_mosi, | ||
| input spim1_miso, | ||
|
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| // hps-usb | ||
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| input usb1_clk, | ||
| output usb1_stp, | ||
| input usb1_dir, | ||
| input usb1_nxt, | ||
| inout [ 7:0] usb1_d, | ||
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| // hps-uart | ||
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| input uart0_rx, | ||
| output uart0_tx, | ||
| inout hps_conv_usb_n, | ||
|
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| // board gpio | ||
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| output [ 7:0] gpio_bd_o, | ||
| input [ 5:0] gpio_bd_i, | ||
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| // hdmi | ||
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| output hdmi_out_clk, | ||
| output hdmi_vsync, | ||
| output hdmi_hsync, | ||
| output hdmi_data_e, | ||
| output [ 23:0] hdmi_data, | ||
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| inout hdmi_i2c_scl, | ||
| inout hdmi_i2c_sda, | ||
|
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| // ad719x | ||
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| inout i2c_sda, | ||
| inout i2c_scl, | ||
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| input ad719x_spi_miso, | ||
| output ad719x_spi_mosi, | ||
| output ad719x_spi_sclk, | ||
| output ad719x_spi_cs_1, | ||
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| output ad719x_sync_n | ||
| ); | ||
|
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| // internal signals | ||
|
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| wire sys_resetn; | ||
| wire [63:0] gpio_i; | ||
| wire [63:0] gpio_o; | ||
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| wire i2c1_scl; | ||
| wire i2c1_scl_oe; | ||
| wire i2c1_sda; | ||
| wire i2c1_sda_oe; | ||
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| wire i2c0_out_data; | ||
| wire i2c0_sda; | ||
| wire i2c0_out_clk; | ||
| wire i2c0_scl_in_clk; | ||
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| // instantiations | ||
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| // unused | ||
| assign gpio_i[63:35] = gpio_o[63:35]; | ||
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| // GPIO outputs | ||
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| assign ad719x_sync_n = gpio_o[33]; | ||
| assign gpio_bd_o[7:0] = gpio_o[7:0]; | ||
|
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| // GPIO inputs | ||
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| assign gpio_i[32] = ad719x_spi_miso; | ||
| assign gpio_i[31:14] = gpio_o[31:14]; | ||
| assign gpio_i[13:8] = gpio_bd_i[5:0]; | ||
|
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| // IO Buffers for I2C | ||
|
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| ALT_IOBUF scl_iobuf ( | ||
| .i(1'b0), | ||
| .oe(i2c1_scl_oe), | ||
| .o(i2c1_scl), | ||
| .io(i2c_scl)); | ||
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| ALT_IOBUF sda_iobuf ( | ||
| .i(1'b0), | ||
| .oe(i2c1_sda_oe), | ||
| .o(i2c1_sda), | ||
| .io(i2c_sda)); | ||
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| ALT_IOBUF scl_video_iobuf ( | ||
| .i(1'b0), | ||
| .oe(i2c0_out_clk), | ||
| .o(i2c0_scl_in_clk), | ||
| .io(hdmi_i2c_scl)); | ||
|
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| ALT_IOBUF sda_video_iobuf ( | ||
| .i(1'b0), | ||
| .oe(i2c0_out_data), | ||
| .o(i2c0_sda), | ||
| .io(hdmi_i2c_sda)); | ||
|
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| system_bd i_system_bd ( | ||
| .sys_clk_clk (sys_clk), | ||
| .sys_hps_h2f_reset_reset_n (sys_resetn), | ||
| .sys_hps_memory_mem_a (ddr3_a), | ||
| .sys_hps_memory_mem_ba (ddr3_ba), | ||
| .sys_hps_memory_mem_ck (ddr3_ck_p), | ||
| .sys_hps_memory_mem_ck_n (ddr3_ck_n), | ||
| .sys_hps_memory_mem_cke (ddr3_cke), | ||
| .sys_hps_memory_mem_cs_n (ddr3_cs_n), | ||
| .sys_hps_memory_mem_ras_n (ddr3_ras_n), | ||
| .sys_hps_memory_mem_cas_n (ddr3_cas_n), | ||
| .sys_hps_memory_mem_we_n (ddr3_we_n), | ||
| .sys_hps_memory_mem_reset_n (ddr3_reset_n), | ||
| .sys_hps_memory_mem_dq (ddr3_dq), | ||
| .sys_hps_memory_mem_dqs (ddr3_dqs_p), | ||
| .sys_hps_memory_mem_dqs_n (ddr3_dqs_n), | ||
| .sys_hps_memory_mem_odt (ddr3_odt), | ||
| .sys_hps_memory_mem_dm (ddr3_dm), | ||
| .sys_hps_memory_oct_rzqin (ddr3_rzq), | ||
| .sys_rst_reset_n (sys_resetn), | ||
| .sys_hps_i2c0_out_data (i2c0_out_data), | ||
| .sys_hps_i2c0_sda (i2c0_sda), | ||
| .sys_hps_i2c0_clk_clk (i2c0_out_clk), | ||
| .sys_hps_i2c0_scl_in_clk (i2c0_scl_in_clk), | ||
| .sys_hps_hps_io_hps_io_emac1_inst_TX_CLK (eth1_tx_clk), | ||
| .sys_hps_hps_io_hps_io_emac1_inst_TXD0 (eth1_tx_d[0]), | ||
| .sys_hps_hps_io_hps_io_emac1_inst_TXD1 (eth1_tx_d[1]), | ||
| .sys_hps_hps_io_hps_io_emac1_inst_TXD2 (eth1_tx_d[2]), | ||
| .sys_hps_hps_io_hps_io_emac1_inst_TXD3 (eth1_tx_d[3]), | ||
| .sys_hps_hps_io_hps_io_emac1_inst_RXD0 (eth1_rx_d[0]), | ||
| .sys_hps_hps_io_hps_io_emac1_inst_MDIO (eth1_mdio), | ||
| .sys_hps_hps_io_hps_io_emac1_inst_MDC (eth1_mdc), | ||
| .sys_hps_hps_io_hps_io_emac1_inst_RX_CTL (eth1_rx_ctl), | ||
| .sys_hps_hps_io_hps_io_emac1_inst_TX_CTL (eth1_tx_ctl), | ||
| .sys_hps_hps_io_hps_io_emac1_inst_RX_CLK (eth1_rx_clk), | ||
| .sys_hps_hps_io_hps_io_emac1_inst_RXD1 (eth1_rx_d[1]), | ||
| .sys_hps_hps_io_hps_io_emac1_inst_RXD2 (eth1_rx_d[2]), | ||
| .sys_hps_hps_io_hps_io_emac1_inst_RXD3 (eth1_rx_d[3]), | ||
| .sys_hps_hps_io_hps_io_sdio_inst_CMD (sdio_cmd), | ||
| .sys_hps_hps_io_hps_io_sdio_inst_D0 (sdio_d[0]), | ||
| .sys_hps_hps_io_hps_io_sdio_inst_D1 (sdio_d[1]), | ||
| .sys_hps_hps_io_hps_io_sdio_inst_CLK (sdio_clk), | ||
| .sys_hps_hps_io_hps_io_sdio_inst_D2 (sdio_d[2]), | ||
| .sys_hps_hps_io_hps_io_sdio_inst_D3 (sdio_d[3]), | ||
| .sys_hps_hps_io_hps_io_usb1_inst_D0 (usb1_d[0]), | ||
| .sys_hps_hps_io_hps_io_usb1_inst_D1 (usb1_d[1]), | ||
| .sys_hps_hps_io_hps_io_usb1_inst_D2 (usb1_d[2]), | ||
| .sys_hps_hps_io_hps_io_usb1_inst_D3 (usb1_d[3]), | ||
| .sys_hps_hps_io_hps_io_usb1_inst_D4 (usb1_d[4]), | ||
| .sys_hps_hps_io_hps_io_usb1_inst_D5 (usb1_d[5]), | ||
| .sys_hps_hps_io_hps_io_usb1_inst_D6 (usb1_d[6]), | ||
| .sys_hps_hps_io_hps_io_usb1_inst_D7 (usb1_d[7]), | ||
| .sys_hps_hps_io_hps_io_usb1_inst_CLK (usb1_clk), | ||
| .sys_hps_hps_io_hps_io_usb1_inst_STP (usb1_stp), | ||
| .sys_hps_hps_io_hps_io_usb1_inst_DIR (usb1_dir), | ||
| .sys_hps_hps_io_hps_io_usb1_inst_NXT (usb1_nxt), | ||
| .sys_hps_hps_io_hps_io_uart0_inst_RX (uart0_rx), | ||
| .sys_hps_hps_io_hps_io_uart0_inst_TX (uart0_tx), | ||
| .sys_hps_hps_io_hps_io_spim1_inst_CLK (spim1_clk), | ||
| .sys_hps_hps_io_hps_io_spim1_inst_MOSI (spim1_mosi), | ||
| .sys_hps_hps_io_hps_io_spim1_inst_MISO (spim1_miso), | ||
| .sys_hps_hps_io_hps_io_spim1_inst_SS0 (spim1_ss0), | ||
| .sys_hps_hps_io_hps_io_gpio_inst_GPIO09 (hps_conv_usb_n), | ||
| .sys_hps_i2c1_sda (i2c1_sda), | ||
| .sys_hps_i2c1_out_data (i2c1_sda_oe), | ||
| .sys_hps_i2c1_clk_clk (i2c1_scl_oe), | ||
| .sys_hps_i2c1_scl_in_clk (i2c1_scl), | ||
| .sys_gpio_bd_in_port (gpio_i[31:0]), | ||
| .sys_gpio_bd_out_port (gpio_o[31:0]), | ||
| .sys_gpio_in_export (gpio_i[63:32]), | ||
| .sys_gpio_out_export (gpio_o[63:32]), | ||
| .sys_spi_MISO (ad719x_spi_miso), | ||
| .sys_spi_MOSI (ad719x_spi_mosi), | ||
| .sys_spi_SCLK (ad719x_spi_sclk), | ||
| .sys_spi_SS_n (ad719x_spi_cs_1), | ||
| .axi_hdmi_tx_0_hdmi_if_h_clk (hdmi_out_clk), | ||
| .axi_hdmi_tx_0_hdmi_if_h24_hsync (hdmi_hsync), | ||
| .axi_hdmi_tx_0_hdmi_if_h24_vsync (hdmi_vsync), | ||
| .axi_hdmi_tx_0_hdmi_if_h24_data_e (hdmi_data_e), | ||
| .axi_hdmi_tx_0_hdmi_if_h24_data (hdmi_data)); | ||
|
|
||
| endmodule |