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JESD204C FEC #1276

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JESD204C FEC #1276

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4b97ec7
Changes to help with timing
Jan 8, 2024
ec0b477
Added support for JESD204C FEC meta mode for RX and TX.
Feb 12, 2024
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62 changes: 62 additions & 0 deletions library/common/ad_mem_dist.v
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Original file line number Diff line number Diff line change
@@ -0,0 +1,62 @@
// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************

`timescale 1ps / 1ps
`default_nettype none

module ad_mem_dist #(
parameter RAM_WIDTH = 32,
parameter RAM_ADDR_BITS = 4
)(
output wire [RAM_WIDTH-1:0] rd_data,
input wire clk,
input wire wr_en,
input wire [RAM_ADDR_BITS-1:0] wr_addr,
input wire [RAM_WIDTH-1:0] wr_data,
input wire [RAM_ADDR_BITS-1:0] rd_addr
);

(* ram_style="distributed" *)
reg [RAM_WIDTH-1:0] ram [(2**RAM_ADDR_BITS)-1:0];

always @(posedge clk)
if (wr_en)
ram[wr_addr] <= wr_data;

assign rd_data = ram[rd_addr];

endmodule

`default_nettype wire
8 changes: 7 additions & 1 deletion library/jesd204/axi_jesd204_common/jesd204_up_common.v
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Original file line number Diff line number Diff line change
Expand Up @@ -91,6 +91,7 @@ module jesd204_up_common #(
output reg [7:0] core_cfg_octets_per_frame = 'h00,
output reg core_cfg_disable_scrambler = 'h00,
output reg core_cfg_disable_char_replacement = 'h00,
output reg [1:0] core_cfg_header_mode = 'h00,
output reg [EXTRA_CFG_WIDTH-1:0] core_extra_cfg = 'h00,

output reg [DEV_EXTRA_CFG_WIDTH-1:0] device_extra_cfg = 'h00,
Expand All @@ -112,6 +113,7 @@ module jesd204_up_common #(
reg [NUM_LANES-1:0] up_cfg_lanes_disable = {NUM_LANES{1'b0}};
reg [NUM_LINKS-1:0] up_cfg_links_disable = {NUM_LINKS{1'b0}};
reg up_cfg_disable_char_replacement = 1'b0;
reg [1:0] up_cfg_header_mode = 1'b0;
reg up_cfg_disable_scrambler = 1'b0;

/* Reset for the register map */
Expand Down Expand Up @@ -201,6 +203,7 @@ module jesd204_up_common #(
core_cfg_links_disable <= up_cfg_links_disable;
core_cfg_disable_scrambler <= up_cfg_disable_scrambler;
core_cfg_disable_char_replacement <= up_cfg_disable_char_replacement;
core_cfg_header_mode <= up_cfg_header_mode;
core_extra_cfg <= up_extra_cfg;
end
end
Expand Down Expand Up @@ -328,7 +331,8 @@ module jesd204_up_common #(
/* 00-09 */ up_cfg_octets_per_multiframe
};
12'h85: up_rdata = {
/* 02-31 */ 30'h00, /* Reserved for future additions */
/* 04-31 */ 30'h00, /* Reserved for future additions */
/* 03-02 */ up_cfg_header_mode, /* 0 - CRC12 ; 1 - CRC3; 2 - FEC; 3 - CMD */
/* 01 */ up_cfg_disable_char_replacement, /* Disable character replacement */
/* 00 */ up_cfg_disable_scrambler /* Disable scrambler */
};
Expand Down Expand Up @@ -372,6 +376,7 @@ module jesd204_up_common #(
up_cfg_beats_per_multiframe <= 'h00;

up_cfg_disable_char_replacement <= 1'b0;
up_cfg_header_mode <= 2'b0;
up_cfg_disable_scrambler <= 1'b0;
end else if (up_wreq == 1'b1) begin
case (up_waddr)
Expand Down Expand Up @@ -401,6 +406,7 @@ module jesd204_up_common #(
{DATA_PATH_WIDTH_LOG2{1'b1}}};
end
12'h085: begin
up_cfg_header_mode <= up_wdata[3:2];
up_cfg_disable_char_replacement <= up_wdata[1];
up_cfg_disable_scrambler <= up_wdata[0];
end
Expand Down
6 changes: 4 additions & 2 deletions library/jesd204/axi_jesd204_common/jesd204_up_sysref.v
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Expand Up @@ -44,7 +44,9 @@

`timescale 1ns/100ps

module jesd204_up_sysref (
module jesd204_up_sysref #(
parameter DATA_PATH_WIDTH_LOG2 = 0
) (
input up_clk,
input up_reset,

Expand Down Expand Up @@ -127,7 +129,7 @@ module jesd204_up_sysref (
end
12'h041: begin
/* Must be aligned to data path width */
up_cfg_lmfc_offset <= up_wdata;
up_cfg_lmfc_offset <= up_wdata[9:DATA_PATH_WIDTH_LOG2];
end
endcase
end
Expand Down
146 changes: 146 additions & 0 deletions library/jesd204/axi_jesd204_common/up_clock_mon.v
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@@ -0,0 +1,146 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************

`timescale 1ns/100ps

module up_clock_mon #(
parameter TOTAL_WIDTH = 32
) (

// processor interface

input up_rstn,
input up_clk,
output reg [TOTAL_WIDTH-1:0] up_d_count,

// device interface

input d_rst,
input d_clk);

// internal registers

reg [15:0] up_count = 'd1;
reg up_count_run = 'd0;
reg up_count_running_m1 = 'd0;
reg up_count_running_m2 = 'd0;
reg up_count_running_m3 = 'd0;
reg d_count_run_m1 = 'd0;
reg d_count_run_m2 = 'd0;
reg d_count_run_m3 = 'd0;
reg [TOTAL_WIDTH:0] d_count = 'd0;

// internal signals

wire up_count_capture_s;
wire d_count_reset_s;

// processor reference

// Capture on the falling edge of running
assign up_count_capture_s = up_count_running_m3 == 1'b1 && up_count_running_m2 == 1'b0;

always @(posedge up_clk) begin
if (up_rstn == 0) begin
up_count_running_m1 <= 1'b0;
up_count_running_m2 <= 1'b0;
up_count_running_m3 <= 1'b0;
end else begin
up_count_running_m1 <= d_count_run_m3;
up_count_running_m2 <= up_count_running_m1;
up_count_running_m3 <= up_count_running_m2;
end
end

always @(posedge up_clk) begin
if (up_rstn == 0) begin
up_d_count <= 'd0;
up_count_run <= 1'b0;
end else begin
if (up_count_running_m3 == 1'b0) begin
up_count_run <= 1'b1;
end else if (up_count == 'h00) begin
up_count_run <= 1'b0;
end

if (up_count_capture_s == 1'b1) begin
up_d_count <= d_count[TOTAL_WIDTH-1:0];
end else if (up_count == 'h00 && up_count_run != up_count_running_m3) begin
up_d_count <= 'h00;
end
end
end

always @(posedge up_clk) begin
if (up_count_run == 1'b0 && up_count_running_m3 == 1'b0) begin
up_count <= 'h01;
end else begin
up_count <= up_count + 1'b1;
end
end

// device free running

// Reset on the rising edge of run
assign d_count_reset_s = d_count_run_m3 == 1'b0 && d_count_run_m2 == 1'b1;

always @(posedge d_clk or posedge d_rst) begin
if (d_rst == 1'b1) begin
d_count_run_m1 <= 1'b0;
d_count_run_m2 <= 1'b0;
d_count_run_m3 <= 1'b0;
end else begin
d_count_run_m1 <= up_count_run;
d_count_run_m2 <= d_count_run_m1;
d_count_run_m3 <= d_count_run_m2;
end
end

always @(posedge d_clk) begin
if (d_count_reset_s == 1'b1) begin
d_count <= 'h00;
end else if (d_count_run_m3 == 1'b1) begin
if (d_count[TOTAL_WIDTH] == 1'b0) begin
d_count <= d_count + 1'b1;
end else begin
d_count <= {TOTAL_WIDTH+1{1'b1}};
end
end
end

endmodule

// ***************************************************************************
// ***************************************************************************
9 changes: 9 additions & 0 deletions library/jesd204/axi_jesd204_common/up_clock_mon_constr.xdc
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@@ -0,0 +1,9 @@

set_property ASYNC_REG true [get_cells -hierarchical -filter {name =~ *up_count_running_m*}]
set_property ASYNC_REG true [get_cells -hierarchical -filter {name =~ *d_count_run_m*}]
set_property ASYNC_REG true [get_cells -hierarchical -filter {name =~ *up_d_count_reg*}]

set_false_path -from [get_cells -hierarchical -filter {name =~ *d_count_run_m3_reg* && IS_SEQUENTIAL}] -to [get_cells -hierarchical -filter {name =~ *up_count_running_m1_reg* && IS_SEQUENTIAL}]
set_false_path -from [get_cells -hierarchical -filter {name =~ *up_count_run_reg* && IS_SEQUENTIAL}] -to [get_cells -hierarchical -filter {name =~ *d_count_run_m1_reg* && IS_SEQUENTIAL}]
set_false_path -from [get_cells -hierarchical -filter {name =~ *d_count_reg* && IS_SEQUENTIAL}] -to [get_cells -hierarchical -filter {name =~ *up_d_count_reg* && IS_SEQUENTIAL}]

19 changes: 13 additions & 6 deletions library/jesd204/axi_jesd204_rx/axi_jesd204_rx.v
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Original file line number Diff line number Diff line change
Expand Up @@ -90,6 +90,7 @@ module axi_jesd204_rx #(
output [7:0] core_cfg_octets_per_frame,
output core_cfg_disable_scrambler,
output core_cfg_disable_char_replacement,
output [1:0] core_cfg_header_mode,
output [7:0] core_cfg_frame_align_err_threshold,

output [9:0] device_cfg_octets_per_multiframe,
Expand All @@ -110,7 +111,7 @@ module axi_jesd204_rx #(
input core_event_frame_alignment_error,
input core_event_unexpected_lane_state_error,

output [6:0] core_ctrl_err_statistics_mask,
output [8:0] core_ctrl_err_statistics_mask,
output core_ctrl_err_statistics_reset,

input [32*NUM_LANES-1:0] core_status_err_statistics_cnt,
Expand All @@ -129,7 +130,9 @@ module axi_jesd204_rx #(

localparam PCORE_VERSION = 32'h00010761; // 1.07.a
localparam PCORE_MAGIC = 32'h32303452; // 204R


localparam DATA_PATH_WIDTH_LOG2 = (DATA_PATH_WIDTH == 8) ? 3 : 2;

/* Register interface signals */
reg [31:0] up_rdata = 'h0;
reg up_wack = 1'b0;
Expand Down Expand Up @@ -246,6 +249,7 @@ module axi_jesd204_rx #(
.core_cfg_links_disable(core_cfg_links_disable),
.core_cfg_disable_scrambler(core_cfg_disable_scrambler),
.core_cfg_disable_char_replacement(core_cfg_disable_char_replacement),
.core_cfg_header_mode(core_cfg_header_mode),

.up_extra_cfg({
/* 00-07 */ up_cfg_frame_align_err_threshold
Expand Down Expand Up @@ -277,9 +281,11 @@ module axi_jesd204_rx #(
.status_synth_params1(status_synth_params1),
.status_synth_params2(status_synth_params2));

jesd204_up_sysref i_up_sysref (
.up_clk(s_axi_aclk),
.up_reset(up_reset),
jesd204_up_sysref #(
.DATA_PATH_WIDTH_LOG2(DATA_PATH_WIDTH_LOG2)
) i_up_sysref (
.up_clk(s_axi_aclk),
.up_reset(up_reset),

.core_clk(core_clk),
.device_clk(device_clk),
Expand All @@ -300,7 +306,8 @@ module axi_jesd204_rx #(

jesd204_up_rx #(
.NUM_LANES(NUM_LANES),
.DATA_PATH_WIDTH(DATA_PATH_WIDTH)
.DATA_PATH_WIDTH(DATA_PATH_WIDTH),
.DATA_PATH_WIDTH_LOG2(DATA_PATH_WIDTH_LOG2)
) i_up_rx (
.up_clk(s_axi_aclk),
.up_reset(up_reset),
Expand Down
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