Add support for AD7606C-16 FMC Daughter Card on Xilinx ZCU102

[bspguy]

PR Description

This commit introduces comprehensive support for the AD7606C-16 FMC based daughter card when used with the Xilinx ZCU102 carrier board. Enhancements include the integration of a Verilog model for accurate simulation and interfacing, updates to the Makefile for streamlined compilation and deployment, and new TCL scripts for improved automation and configuration processes. These changes enable seamless integration and utilization of the AD7606C-16 FMC daughter card with the ZCU102, facilitating advanced data acquisition and processing capabilities for embedded projects.

PR Type

• Bug fix (change that fixes an issue)
• New feature (change that adds new functionality)
• Breaking change (has dependencies in other repos or will cause CI to fail)

PR Checklist

• I have followed the code style guidelines
• I have performed a self-review of changes
• I have compiled all hdl projects and libraries affected by this PR
• I have tested in hardware affected projects, at least on relevant boards
• I have commented my code, at least hard-to-understand parts
• I have signed off all commits from this PR
• I have updated the documentation (wiki pages, ReadMe files, Copyright etc)
• I have not introduced new Warnings/Critical Warnings on compilation
• I have added new hdl testbenches or updated existing ones

[bspguy]

@acostina @PopPaul2021 @AndreiGrozav
Please review
Thanks
Roy