projects/scripts/adi_board: Updated ad_cpu interconnect #1337
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IstvanZsSzekely
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acostina,
AndreiGrozav,
PopPaul2021,
gastmaier and
sarpadi
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acostina
previously approved these changes
Jun 14, 2024
- Added option to cascade interconnects in if 16 or more modules are connected to the CPU - Added option to enable cascading, by default it is disabled Signed-off-by: Istvan-Zsolt Szekely <[email protected]>
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PR Description
On testbenches, if more than 16 interconnects are used, then the validation fail, since one of the Master interfaces is always AXI4Full (DDR). In order to fix this issue, cascading interconnects are automatically created when connecting IPs to the CPU.
Added option to cascade interconnects in testbenches if 16 or more modules are connected to the CPU.
Added an additional variable to choose between a cascaded or non-cascaded interconnect option for HDL. For Testbenches it's automatically set to be cascaded.
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