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SPI Engine: execution improvements #1499

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Nov 14, 2024
Merged

SPI Engine: execution improvements #1499

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ed1483a
SPI Engine Execution: split counters
LBFFilho Aug 15, 2024
3c56531
SPI Engine Execution: split shift register logic
LBFFilho Aug 15, 2024
88ed47a
SPI Engine Execution: pipeline sdo alignment
LBFFilho Aug 15, 2024
831e115
Guidelines fix
LBFFilho Nov 11, 2024
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14 changes: 8 additions & 6 deletions library/spi_engine/spi_engine_execution/spi_engine_execution.v
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Original file line number Diff line number Diff line change
Expand Up @@ -96,7 +96,6 @@ module spi_engine_execution #(
localparam BIT_COUNTER_CLEAR = {{8{1'b1}}, {BIT_COUNTER_WIDTH{1'b0}}, 1'b1};

reg sclk_int = 1'b0;
wire sdo_int_s;
reg sdo_t_int = 1'b0;

reg idle;
Expand All @@ -106,7 +105,6 @@ module spi_engine_execution #(
reg clk_div_last;

reg [7:0] sleep_counter;
wire [1:0] cs_sleep_counter = sleep_counter[1:0];
reg [(BIT_COUNTER_WIDTH-1):0] bit_counter;
reg [7:0] transfer_counter;
reg ntx_rx;
Expand All @@ -117,12 +115,9 @@ module spi_engine_execution #(
reg wait_for_io = 1'b0;
reg transfer_active = 1'b0;

wire last_bit;
wire first_bit;
reg last_transfer;
reg [7:0] word_length = DATA_WIDTH;
reg [7:0] left_aligned = 8'b0;
wire end_of_word;

assign first_bit = ((bit_counter == 'h0) || (bit_counter == word_length));

Expand All @@ -138,6 +133,12 @@ module spi_engine_execution #(
reg sdo_enabled = 1'b0;
reg sdi_enabled = 1'b0;

wire sdo_int_s;

wire last_bit;
wire first_bit;
wire end_of_word;

wire [2:0] inst = cmd[14:12];
wire [2:0] inst_d1 = cmd_d1[14:12];

Expand All @@ -152,6 +153,7 @@ module spi_engine_execution #(
wire trigger_tx;
wire trigger_rx;

wire [1:0] cs_sleep_counter = sleep_counter[1:0];
wire sleep_counter_compare;
wire cs_sleep_counter_compare;
wire cs_sleep_early_exit;
Expand All @@ -169,7 +171,7 @@ module spi_engine_execution #(

spi_engine_execution_shiftreg #(
.DEFAULT_SPI_CFG(DEFAULT_SPI_CFG),
.DATA_WIDTH(DATA_WIDTH), // Valid data widths values are 8/16/24/32
.DATA_WIDTH(DATA_WIDTH),
.NUM_OF_SDI(NUM_OF_SDI),
.SDI_DELAY(SDI_DELAY),
.ECHO_SCLK(ECHO_SCLK),
Expand Down
72 changes: 37 additions & 35 deletions library/spi_engine/spi_engine_execution/spi_engine_execution_shiftreg.v
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Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2015-2024 Analog Devices, Inc. All rights reserved.
// Copyright (C) 2024 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
Expand Down Expand Up @@ -38,54 +38,56 @@
module spi_engine_execution_shiftreg #(

parameter DEFAULT_SPI_CFG = 0,
parameter DATA_WIDTH = 8, // Valid data widths values are 8/16/24/32
parameter DATA_WIDTH = 8,
parameter NUM_OF_SDI = 1,
parameter [1:0] SDI_DELAY = 2'b00,
parameter ECHO_SCLK = 0,
parameter [2:0]CMD_TRANSFER = 3'b000
) (
input clk,
input resetn,
input clk,
input resetn,

// spi io
input [NUM_OF_SDI-1:0] sdi,
output sdo_int,
input echo_sclk,
input [NUM_OF_SDI-1:0] sdi,
output sdo_int,
input echo_sclk,

// spi data
input [(DATA_WIDTH-1):0] sdo_data,
input sdo_data_valid,
output reg sdo_data_ready,
output [(NUM_OF_SDI * DATA_WIDTH-1):0] sdi_data,
output reg sdi_data_valid,
input sdi_data_ready,
input [(DATA_WIDTH-1):0] sdo_data,
input sdo_data_valid,
output reg sdo_data_ready,

output [(NUM_OF_SDI * DATA_WIDTH-1):0] sdi_data,
output reg sdi_data_valid,
input sdi_data_ready,

// cfg and status
input sdo_enabled,
input sdi_enabled,
input [15:0] current_cmd,
input sdo_idle_state,
input [7:0] left_aligned,
input [7:0] word_length,
input sdo_enabled,
input sdi_enabled,
input [15:0] current_cmd,
input sdo_idle_state,
input [ 7:0] left_aligned,
input [ 7:0] word_length,

// timing from main fsm
input sample_sdo,
output reg sdo_io_ready,
input transfer_active,
input trigger_tx,
input trigger_rx,
input first_bit,
input cs_activate,
output end_of_sdi_latch
input sample_sdo,
output reg sdo_io_ready,
input transfer_active,
input trigger_tx,
input trigger_rx,
input first_bit,
input cs_activate,
output end_of_sdi_latch
);

reg [7:0] sdi_counter = 8'b0;
reg [ 7:0] sdi_counter = 8'b0;
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reg [(DATA_WIDTH-1):0] data_sdo_shift = 'h0;
reg [ SDI_DELAY+1:0] trigger_rx_d = {(SDI_DELAY+2){1'b0}};
reg [(DATA_WIDTH-1):0] aligned_sdo_data, sdo_data_d;
wire last_sdi_bit;
reg [SDI_DELAY+1:0] trigger_rx_d = {(SDI_DELAY+2){1'b0}};
wire trigger_rx_s;
wire [2:0] current_instr = current_cmd[14:12];

wire trigger_rx_s;
wire [2:0] current_instr = current_cmd[14:12];
wire last_sdi_bit;

always @(posedge clk) begin
if (resetn == 1'b0) begin
Expand Down Expand Up @@ -130,7 +132,6 @@ module spi_engine_execution_shiftreg #(
assign sdo_int = data_sdo_shift[DATA_WIDTH-1];
assign sdo_toshiftreg = (transfer_active && trigger_tx && first_bit && sdo_enabled);


// In case of an interface with high clock rate (SCLK > 50MHz), the latch of
// the SDI line can be delayed with 1, 2 or 3 SPI core clock cycle.
// Taking the fact that in high SCLK frequencies the pre-scaler most likely will
Expand Down Expand Up @@ -228,7 +229,7 @@ module spi_engine_execution_shiftreg #(
// sdi_data_valid is synchronous to SPI clock, so synchronize the
// last_sdi_bit to SPI clock

reg [3:0] last_sdi_bit_m = 4'b0; //FIXME: why not just use sync_bits?
reg [3:0] last_sdi_bit_m = 4'b0;
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always @(posedge clk) begin
if (cs_activate) begin
last_sdi_bit_m <= 4'b0;
Expand All @@ -254,7 +255,8 @@ module spi_engine_execution_shiftreg #(
num_of_transfers <= 8'b0;
end else begin
if (current_instr == CMD_TRANSFER) begin
num_of_transfers <= current_cmd[7:0] + 1'b1; // current_cmd contains the NUM_OF_TRANSFERS - 1
// current_cmd contains the NUM_OF_TRANSFERS - 1
num_of_transfers <= current_cmd[7:0] + 1'b1;
end
end
end
Expand Down
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