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library: xilinx: common: ad_mmcm_drp: Add Versal family support #1507

Merged
merged 1 commit into from
Nov 27, 2024
Merged

library: xilinx: common: ad_mmcm_drp: Add Versal family support #1507

merged 1 commit into from
Nov 27, 2024

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bluncan
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@bluncan bluncan commented Nov 6, 2024

PR Description

Adds mmcme5 instantiation for Versal boards inside ad_mmcm_drp. This allows us to use the axi_clkgen IP on Versal FPGAs as well.

PR Type

  • Bug fix (change that fixes an issue)
  • New feature (change that adds new functionality)
  • Breaking change (has dependencies in other repos or will cause CI to fail)

PR Checklist

  • I have followed the code style guidelines
  • I have performed a self-review of changes
  • I have compiled all hdl projects and libraries affected by this PR
  • I have tested in hardware affected projects, at least on relevant boards
  • I have commented my code, at least hard-to-understand parts
  • I have signed off all commits from this PR
  • I have updated the documentation (wiki pages, ReadMe files, Copyright etc)
  • I have not introduced new Warnings/Critical Warnings on compilation
  • I have added new hdl testbenches or updated existing ones

@bluncan bluncan merged commit 445631d into main Nov 27, 2024
3 of 5 checks passed
@bluncan bluncan deleted the dev_versal_clkgen_support branch November 27, 2024 09:33
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@FilipG24 FilipG24 FilipG24 approved these changes

@acostina acostina acostina approved these changes

@AndreiGrozav AndreiGrozav Awaiting requested review from AndreiGrozav AndreiGrozav is a code owner

@PopPaul2021 PopPaul2021 Awaiting requested review from PopPaul2021 PopPaul2021 is a code owner

@gastmaier gastmaier Awaiting requested review from gastmaier gastmaier is a code owner

@sarpadi sarpadi Awaiting requested review from sarpadi sarpadi is a code owner

@IuliaCMoldovan IuliaCMoldovan Awaiting requested review from IuliaCMoldovan

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3 participants
@bluncan @acostina @FilipG24