docs: PR review changes 2

docs/projects/project_based/template/index.rst

@@ -123,7 +123,7 @@ Building the test bench
 The testbench is built upon ADI's generic HDL reference design framework.
 ADI does not distribute compiled files of these projects so they must be built
 from the sources available :git-hdl:`here </>` and :git-testbenches:`here </>`,
-with the specified hierarchy described :ref:`build_tb/set_up_tb_repo </>``.
+with the specified hierarchy described :ref:`build_tb set_up_tb_repo`.
 To get the source you must
 `clone <https://git-scm.com/book/en/v2/Git-Basics-Getting-a-Git-Repository>`__
 the HDL repository, and then build the project as follows:.

docs/user_guide/build_tb.rst

@@ -94,11 +94,6 @@ the project. This option gives you the ability to build only the configuration
 that you're interested in, without building the rest of the available
 configurations, as well as running the chosen test program, if it is the case.
 
-.. note::
-
-   PR note: **system_project.tcl** doesn't necessarily tell which are the
-   configurations/parameters that can be used to build the project.
-
 If parameters were used, the result of the build will be in a folder under runs/,
 named by the configuration used.
 

docs/user_guide/git_repository.rst

@@ -64,7 +64,7 @@ The repository is divided into 5 separate sections:
 -  **docs** with our GitHubIO documentation and regmap source files
 -  **library** with all the Analog Devices Inc. proprietary IP cores and
    hdl modules, which are required to build the projects
--  **scripts** with our environment scripts that set tools versions, etc.
+-  **scripts** with scripts and makefiles to build and run the testbench
 -  **testbenches** with all the currently supported testbenches
 
 

docs/user_guide/introduction.rst

@@ -15,7 +15,7 @@ desired). Furthermore, all ADI developed and supported IPs are presented in deta
 At the same time, the user guides are not intended to be a guide for any third
 party tool. To understand and use the HDL framework efficiently the user needs
 to have a **solid understanding on how an FPGA works, to be familiar with all
-the design tools and flows, testbenches, SystemVerilog and classes.**. These
+the design tools and flows, testbenches, SystemVerilog and classes**. These
 testbenches are not using UVM, however, some ideas are used from the
 verification standard, meaning that a high level overview of UVM can be useful
 in understanding the design structure.