V3: Update scoreboard, clean-up

Signed-off-by: Jorge Marques <[email protected]>

common/sv/dma_trans.sv

@@ -1,6 +1,6 @@
 // ***************************************************************************
 // ***************************************************************************
-// Copyright 2014 - 2018 (c) Analog Devices, Inc. All rights reserved.
+// Copyright 2014 - 2018, 2024 (c) Analog Devices, Inc. All rights reserved.
 //
 // In this HDL repository, there are many different and unique modules, consisting
 // of various HDL (Verilog or VHDL) components. The individual modules are
@@ -396,7 +396,7 @@ package dma_trans_pkg;
      return sa;
     endfunction
 
-  endclass
+  endclass : dma_partial_2d_segment
 
   //==========================================================================
   /*

common/sv/dmac_api.sv

@@ -1,6 +1,6 @@
 // ***************************************************************************
 // ***************************************************************************
-// Copyright 2014 - 2018 (c) Analog Devices, Inc. All rights reserved.
+// Copyright 2014 - 2018, 2024 (c) Analog Devices, Inc. All rights reserved.
 //
 // In this HDL repository, there are many different and unique modules, consisting
 // of various HDL (Verilog or VHDL) components. The individual modules are
@@ -79,11 +79,11 @@ package dmac_api_pkg;
       p.USE_EXT_SYNC = `GET_DMAC_INTERFACE_DESCRIPTION_1_USE_EXT_SYNC(val);
       p.HAS_AUTORUN = `GET_DMAC_INTERFACE_DESCRIPTION_1_HAS_AUTORUN(val);
       this.axi_write(GetAddrs(DMAC_X_LENGTH),
-                        `SET_DMAC_X_LENGTH_X_LENGTH(32'h0));
+                     `SET_DMAC_X_LENGTH_X_LENGTH(32'h0));
       this.axi_read(GetAddrs(DMAC_X_LENGTH), val);
       p.DMA_LENGTH_ALIGN = `GET_DMAC_X_LENGTH_X_LENGTH(val)+1;
       this.axi_write(GetAddrs(DMAC_Y_LENGTH),
-                        `SET_DMAC_Y_LENGTH_Y_LENGTH(32'hFFFFFFFF));
+                     `SET_DMAC_Y_LENGTH_Y_LENGTH(32'hFFFFFFFF));
       this.axi_read(GetAddrs(DMAC_Y_LENGTH), val);
       if (val==0) begin
         p.DMA_2D_TRANSFER = 0;
@@ -123,36 +123,36 @@ package dmac_api_pkg;
     // -----------------
     task enable_dma();
       this.axi_write(GetAddrs(DMAC_CONTROL),
-                        `SET_DMAC_CONTROL_ENABLE(1));
+                     `SET_DMAC_CONTROL_ENABLE(1));
     endtask : enable_dma
 
     // -----------------
     //
     // -----------------
     task disable_dma();
       this.axi_write(GetAddrs(DMAC_CONTROL),
-                        `SET_DMAC_CONTROL_PAUSE(0));
+                     `SET_DMAC_CONTROL_PAUSE(0));
     endtask : disable_dma
 
     // -----------------
     //
     // -----------------
     task set_control(input bit[3:0] control);
       this.axi_write(GetAddrs(DMAC_CONTROL),
-                        `SET_DMAC_CONTROL_ENABLE(control[0]) |
-                        `SET_DMAC_CONTROL_PAUSE(control[1]) |
-                        `SET_DMAC_CONTROL_HWDESC(control[2]) |
-                        `SET_DMAC_CONTROL_FRAMELOCK(control[3]));
+                     `SET_DMAC_CONTROL_ENABLE(control[0]) |
+                     `SET_DMAC_CONTROL_PAUSE(control[1]) |
+                     `SET_DMAC_CONTROL_HWDESC(control[2]) |
+                     `SET_DMAC_CONTROL_FRAMELOCK(control[3]));
     endtask : set_control
 
     // -----------------
     //
     // -----------------
     task set_flags(input bit[3:0] flags);
       this.axi_write(GetAddrs(DMAC_FLAGS),
-                        `SET_DMAC_FLAGS_CYCLIC(flags[0]) |
-                        `SET_DMAC_FLAGS_TLAST(flags[1]) |
-                        `SET_DMAC_FLAGS_PARTIAL_REPORTING_EN(flags[2]));
+                     `SET_DMAC_FLAGS_CYCLIC(flags[0]) |
+                     `SET_DMAC_FLAGS_TLAST(flags[1]) |
+                     `SET_DMAC_FLAGS_PARTIAL_REPORTING_EN(flags[2]));
     endtask : set_flags
 
     // -----------------
@@ -186,7 +186,7 @@ package dmac_api_pkg;
     // -----------------
     task transfer_start;
       this.axi_write(GetAddrs(DMAC_TRANSFER_SUBMIT),
-                        `SET_DMAC_TRANSFER_SUBMIT_TRANSFER_SUBMIT(1));
+                     `SET_DMAC_TRANSFER_SUBMIT_TRANSFER_SUBMIT(1));
       `INFO(("Transfer start"));
     endtask : transfer_start
 
@@ -195,15 +195,15 @@ package dmac_api_pkg;
     // -----------------
     task set_dest_addr(input int xfer_addr);
       this.axi_write(GetAddrs(DMAC_DEST_ADDRESS),
-                        `SET_DMAC_DEST_ADDRESS_DEST_ADDRESS(xfer_addr));
+                     `SET_DMAC_DEST_ADDRESS_DEST_ADDRESS(xfer_addr));
     endtask : set_dest_addr
 
     // -----------------
     //
     // -----------------
     task set_src_addr(input int xfer_addr);
       this.axi_write(GetAddrs(DMAC_SRC_ADDRESS),
-                        `SET_DMAC_SRC_ADDRESS_SRC_ADDRESS(xfer_addr));
+                     `SET_DMAC_SRC_ADDRESS_SRC_ADDRESS(xfer_addr));
     endtask : set_src_addr
 
     // -----------------
@@ -213,9 +213,9 @@ package dmac_api_pkg;
       input int xfer_length_x,
       input int xfer_length_y);
       this.axi_write(GetAddrs(DMAC_X_LENGTH),
-                        `SET_DMAC_X_LENGTH_X_LENGTH(xfer_length_x));
+                     `SET_DMAC_X_LENGTH_X_LENGTH(xfer_length_x));
       this.axi_write(GetAddrs(DMAC_Y_LENGTH),
-                        `SET_DMAC_Y_LENGTH_Y_LENGTH(xfer_length_y));
+                     `SET_DMAC_Y_LENGTH_Y_LENGTH(xfer_length_y));
     endtask : set_lengths
 
     // -----------------

common/sv/io_vip/io_vip.sv

@@ -1,6 +1,6 @@
 // ***************************************************************************
 // ***************************************************************************
-// Copyright 2014 - 2018 (c) Analog Devices, Inc. All rights reserved.
+// Copyright 2024 (c) Analog Devices, Inc. All rights reserved.
 //
 // In this HDL repository, there are many different and unique modules, consisting
 // of various HDL (Verilog or VHDL) components. The individual modules are
@@ -34,12 +34,12 @@
 // ***************************************************************************
 
 module io_vip #(
-  parameter MODE = 1, // 1 - driver, 0 - monitor
+  parameter MODE = 1, // 1 - master, 0 - slave
   parameter WIDTH = 1
 )(
   input  clk,
-  input  in,
-  output out
+  input  [WIDTH-1:0] in,
+  output [WIDTH-1:0] out
 );
 
   io_vip_if #(
@@ -49,9 +49,8 @@ module io_vip #(
     .clk(clk)
   );
 
-  generate if (MODE) begin
-    assign out = IF.io;
-  end else begin
+  assign out = IF.io;
+  generate if (~MODE) begin
     assign IF.io = in;
   end
   endgenerate

common/sv/io_vip/io_vip_if.sv

@@ -1,6 +1,6 @@
 // ***************************************************************************
 // ***************************************************************************
-// Copyright 2014 - 2024 (c) Analog Devices, Inc. All rights reserved.
+// Copyright 2024 (c) Analog Devices, Inc. All rights reserved.
 //
 // In this HDL repository, there are many different and unique modules, consisting
 // of various HDL (Verilog or VHDL) components. The individual modules are
@@ -34,18 +34,18 @@
 // ***************************************************************************
 
 interface io_vip_if #(
-  int MODE = 0, // 1 - driver, 0 - monitor
+  int MODE = 0, // 1 - master, 0 - slave
       WIDTH = 1
 ) (
   input bit clk
 );
 
   logic [WIDTH-1:0] io = 0;
 
-  // Driver functions
+  // Master functions
   function void set_io(int o);
     if (MODE === 0) begin
-      $display("[ERROR] %0t Unsupported in monitor mode", $time);
+      $display("[ERROR] %0t Unsupported in slave mode", $time);
       $finish;
     end else begin
       io <= o[WIDTH-1:0];
@@ -58,7 +58,7 @@ interface io_vip_if #(
     set_io(o);
   endtask
 
-  // Monitor functions
+  // Slave functions
   function int get_io();
     return io;
   endfunction

common/sv/io_vip/io_vip_ip.tcl

@@ -22,8 +22,6 @@ ipx::remove_all_bus_interface [ipx::current_core]
 
 adi_set_ports_dependency "in" \
       "(spirit:decode(id('MODELPARAM_VALUE.MODE')) = 0)"
-adi_set_ports_dependency "out" \
-      "(spirit:decode(id('MODELPARAM_VALUE.MODE')) = 1)"
 
 set cc [ipx::current_core]
 

common/sv/io_vip/io_vip_pkg.ttcl

@@ -1,5 +1,5 @@
 ###############################################################################
-## Copyright (C) 2018-2024 Analog Devices, Inc. All rights reserved.
+## Copyright (C) 2024 Analog Devices, Inc. All rights reserved.
 # SPDX short identifier: ADIBSD
 ###############################################################################
 

common/sv/m_axis_sequencer.sv

@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //

dma_flock/environment.sv

@@ -79,7 +79,6 @@ package environment_pkg;
     // Register accessors
 
     dma_transfer_group trans_q[$];
-    bit done = 0;
 
     scoreboard scrb;
 
@@ -95,10 +94,10 @@ package environment_pkg;
 
       virtual interface axi_vip_if #(`AXI_VIP_IF_PARAMS(test_harness, mng_axi_vip)) mng_vip_if,
       virtual interface axi_vip_if #(`AXI_VIP_IF_PARAMS(test_harness, ddr_axi_vip)) ddr_vip_if,
-    `ifdef HAS_XIL_VDMA
+      `ifdef HAS_XIL_VDMA
       virtual interface axi4stream_vip_if #(`AXIS_VIP_IF_PARAMS(test_harness, ref_src_axis_vip)) ref_src_axis_vip_if,
       virtual interface axi4stream_vip_if #(`AXIS_VIP_IF_PARAMS(test_harness, ref_dst_axis_vip)) ref_dst_axis_vip_if,
-    `endif
+      `endif
       virtual interface axi4stream_vip_if #(`AXIS_VIP_IF_PARAMS(test_harness, src_axis_vip)) src_axis_vip_if,
       virtual interface axi4stream_vip_if #(`AXIS_VIP_IF_PARAMS(test_harness, dst_axis_vip)) dst_axis_vip_if
     );
@@ -112,18 +111,18 @@ package environment_pkg;
       // Creating the agents
       src_axis_agent = new("Src AXI stream agent", src_axis_vip_if);
       dst_axis_agent = new("Dest AXI stream agent", dst_axis_vip_if);
-    `ifdef HAS_XIL_VDMA
+      `ifdef HAS_XIL_VDMA
       ref_src_axis_agent = new("Ref Src AXI stream agent", ref_src_axis_vip_if);
       ref_dst_axis_agent = new("Ref Dest AXI stream agent", ref_dst_axis_vip_if);
-    `endif
+      `endif
 
       // Creating the sequencers
       src_axis_seq = new(src_axis_agent);
       dst_axis_seq = new(dst_axis_agent);
-    `ifdef HAS_XIL_VDMA
+      `ifdef HAS_XIL_VDMA
       ref_src_axis_seq = new(ref_src_axis_agent);
       ref_dst_axis_seq = new(ref_dst_axis_agent);
-    `endif
+      `endif
 
     scrb = new;
 
@@ -143,10 +142,10 @@ package environment_pkg;
 
       src_axis_agent.start_master();
       dst_axis_agent.start_slave();
-    `ifdef HAS_XIL_VDMA
+      `ifdef HAS_XIL_VDMA
       ref_src_axis_agent.start_master();
       ref_dst_axis_agent.start_slave();
-    `endif
+      `endif
 
     endtask
 
@@ -157,16 +156,14 @@ package environment_pkg;
     //============================================================================
     task test();
       super.test();
-      fork
-        src_axis_seq.run();
-        `ifdef HAS_XIL_VDMA
-        ref_src_axis_seq.run();
-        `endif
-        // DEST AXIS does not have to run, scoreboard connects and
-        // gathers packets from the agent
-        scrb.run();
-        test_c_run();
-      join_none
+      src_axis_seq.run();
+      `ifdef HAS_XIL_VDMA
+      ref_src_axis_seq.run();
+      `endif
+      // DEST AXIS does not have to run, scoreboard connects and
+      // gathers packets from the agent
+      scrb.run();
+      test_c_run();
     endtask
 
     //============================================================================