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docs: Update prj_based template
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@StancaPop
StancaPop committed Nov 29, 2024
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211 changes: 199 additions & 12 deletions docs/testbenches/project_based/template/index.rst
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Expand Up @@ -8,33 +8,44 @@ Project based test bench template
Overview
-------------------------------------------------------------------------------

**\*This section must contain: the purpose of the testbench/ type of interface
it's validating, the corresponding hdl project and the HDL Github documentation
page.**\ \*

Block design
-------------------------------------------------------------------------------

**\*Mention the HDL and SV components of the testbench .**\ \*

Block diagram
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

..
MUST: Use SVG format for the diagram
If the testbench has multiple ways of configuration, then make subsections to
this section and show the default configuration and some other popular modes.

..
TIP: Block diagrams should contain subtitles only if there are at least two
different diagrams
\**\* KEEP THIS PARAGRAPH \**\*
The data path and clock domains are depicted in the below diagram:

.. image:: ../template/project_based_template_bd.svg
:width: 800
:align: center
:alt: Template/Testbench block diagram

\*\* MUST: Use SVG format for the diagram \*\*

\*\* TIP: Block diagrams should contain subtitles only if there are at least two
different diagrams \*\*

Configuration parameters and modes
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

..
MENTION IF ANY MODES ARE AVAILABLE FOR CONFIGURATION
\**\* MENTION IF ANY MODES ARE AVAILABLE FOR CONFIGURATION \**\*

Build parameters
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

\**\* THIS IS JUST AN EXAMPLE \**\*

The following are the parameters of this project that can be configured:

- CLK_MODE: defines clocking mode of the device's digital interface:
Expand All @@ -53,8 +64,9 @@ The following are the parameters of this project that can be configured:
Configuration files
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

..
MENTION IF ANY CONFIGURATION FILES ARE AVAILABLE FOR TESTS
\**\* MENTION IF ANY CONFIGURATION FILES ARE AVAILABLE\**\*

\**\* THIS IS JUST AN EXAMPLE \**\*

The following are available configurations for the test bench:

Expand Down Expand Up @@ -119,12 +131,64 @@ cfg_pi test_program_pi make CFG=cfg_pi TST=test_program_pi
Clock scheme
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

\**\* MENTION IF ANY CLOCKING CONFIGURATIONS ARE BEING USED\**\*

CPU/Memory interconnects addresses
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

\**\* THIS IS JUST AND EXAMPLE \**\*

Below are the CPU/Memory interconnect addresses used in this project:

===================== ===========
Instance Address
===================== ===========
spi_ad7616_axi_regmap 0x44A0_0000
axi_ad7606x_dma 0x44A3_0000
spi_clkgen 0x44A7_0000
ad7606_pwm_gen 0x44B0_0000
===================== ===========

Interrupts
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

\**\* THIS IS JUST AND EXAMPLE \**\*

Below are the Programmable Logic interrupts used in this project:

=============== ===
Instance name HDL
=============== ===
axi_ad7606_dma 13
spi_ad7606 12
=============== ===

Test stimulus
-------------------------------------------------------------------------------

\**\* LIST AND EXPLAIN ALL THE TESTS COMPRISED IN THE test_program FILE \**\*

\**\* THIS IS JUST AND EXAMPLE \**\*

The test program is structured into several tests as follows:

Environment Bringup
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

The steps of the environment bringup are:

* Create the environment
* Start the environment
* Start the clocks
* Assert the resets

Sanity Test
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

This test is used to check the communication with the AXI REGMAP module of the
AD7606 SPI Engine interface, by reading the core VERSION register, along with
writing and reading the SCRATCH register.

Building the test bench
-------------------------------------------------------------------------------

Expand Down Expand Up @@ -184,16 +248,139 @@ Then the subfolder under ``runs`` name will be:

``cfg_pi``

Test stimulus
-------------------------------------------------------------------------------

Resources
-------------------------------------------------------------------------------

HDL related dependencies
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

\**\* THIS IS JUST AND EXAMPLE \**\*

.. list-table::
:widths: 30 45 25
:header-rows: 1

* - IP name
- Source code link
- Documentation link
* - SYNC_BITS
- :git-hdl:`library/util_cdc/sync_bits.v <library/util_cdc/sync_bits.v>` **
- ---
* - AD_EDGE_DETECT
- :git-hdl:`library/common/ad_edge_detect.v <library/common/ad_edge_detect.v>`
- ---
* - AXI_AD7606x
- :git-hdl:`library/axi_ad7606x <library/axi_ad7606x>` *
- :dokuwiki:`[Wiki] <resources/fpga/docs/axi_ad7606x>`
* - AXI_CLKGEN
- :git-hdl:`library/axi_clkgen <library/axi_clkgen>`
- :external+hdl:ref:`here <axi_clkgen>`
* - AXI_DMAC
- :git-hdl:`library/axi_dmac <library/axi_dmac>`
- :external+hdl:ref:`here <axi_dmac>`
* - AXI_HDMI_TX
- :git-hdl:`library/axi_hdmi_tx <library/axi_hdmi_tx>`
- :external+hdl:ref:`here <axi_hdmi_tx>`
* - AXI_I2S_ADI
- :git-hdl:`library/axi_i2s_adi <library/axi_i2s_adi>`
- ---
* - AXI_PWM_GEN
- :git-hdl:`library/axi_pwm_gen <library/axi_pwm_gen>`
- :external+hdl:ref:`here <axi_pwm_gen>`
* - AXI_SPDIF_TX
- :git-hdl:`library/axi_spdif_tx <library/axi_spdif_tx>`
- ---
* - AXI_SYSID
- :git-hdl:`library/axi_sysid <library/axi_sysid>`
- :external+hdl:ref:`here <axi_sysid>`
* - AXI_SPI_ENGINE
- :git-hdl:`library/spi_engine/axi_spi_engine <library/spi_engine/axi_spi_engine>` **
- :external+hdl:ref:`here <spi_engine axi>`
* - SPI_ENGINE_EXECUTION
- :git-hdl:`library/spi_engine/spi_engine_execution <library/spi_engine/spi_engine_execution>` **
- :external+hdl:ref:`here <spi_engine execution>`
* - SPI_ENGINE_INTERCONNECT
- :git-hdl:`library/spi_engine/spi_engine_interconnect <library/spi_engine/spi_engine_interconnect>` **
- :external+hdl:ref:`here <spi_engine interconnect>`
* - SPI_ENGINE_OFFLOAD
- :git-hdl:`library/spi_engine/spi_engine_offload <library/spi_engine/spi_engine_offload>` **
- :external+hdl:ref:`here <spi_engine offload>`
* - SYSID_ROM
- :git-hdl:`library/sysid_rom <library/sysid_rom>`
- :external+hdl:ref:`here <axi_sysid>`
* - UTIL_I2C_MIXER
- :git-hdl:`library/util_i2c_mixer <library/util_i2c_mixer>`
- ---
* - UTIL_CPACK2
- :git-hdl:`library/util_pack/util_cpack2 <library/util_pack/util_cpack2>` *
- :external+hdl:ref:`here <util_cpack2>`

.. admonition:: Legend
:class: note

- ``*`` instantiated only for INTF=0 (parallel interface)
- ``**`` instantiated only for INTF=1 (serial interface)


Testbenches related dependencies
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

.. include:: ../../common/dependency_common.rst

Testbench specific dependencies:

\**\* THIS IS JUST AND EXAMPLE \**\*

.. list-table::
:widths: 30 45 25
:header-rows: 1

* - SV dependency name
- Source code link
- Documentation link
* - ADI_REGMAP_ADC_PKG
- :git-testbenches:`library/regmaps/adi_regmap_adc_pkg.sv`
- ---
* - ADI_REGMAP_COMMON_PKG
- :git-testbenches:`library/regmaps/adi_regmap_common_pkg.sv`
- ---
* - ADI_REGMAP_DMAC_PKG
- :git-testbenches:`library/regmaps/adi_regmap_dmac_pkg.`
- ---
* - ADI_REGMAP_PKG
- :git-testbenches:`library/regmaps/adi_regmap_pkg.sv`
- ---
* - ADI_REGMAP_PWM_GEN_PKG
- :git-testbenches:`library/regmaps/adi_regmap_pwm_gen_pkg.sv`
- ---
* - DMA_TRANS
- :git-testbenches:`library/drivers/dmac/dma_trans.sv`
- ---
* - DMAC_API
- :git-testbenches:`library/drivers/dmac/dmac_api.sv`
- ---
* - LOGGER_PKG
- :git-testbenches:`library/utilities/logger_pkg.sv`
- ---
* - M_AXI_SEQUENCER
- :git-testbenches:`library/vip/amd/m_axi_sequencer.sv`
- ---
* - M_AXIS_SEQUENCER
- :git-testbenches:`library/vip/amd/m_axis_sequencer.sv`
- ---
* - REG_ACCESSOR
- :git-testbenches:`library/regmaps/reg_accessor.sv`
- ---
* - S_AXI_SEQUENCER
- :git-testbenches:`library/vip/amd/s_axi_sequencer.sv`
- ---
* - S_AXIS_SEQUENCER
- :git-testbenches:`library/vip/amd/s_axis_sequencer.sv`
- ---
* - UTILS
- :git-testbenches:`library/utilities/utils.svh`
- ---

.. include:: ../../../common/more_information.rst

.. include:: ../../../common/support.rst

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