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dbSta: clang-tidy
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Signed-off-by: Matt Liberty <[email protected]>
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maliberty committed Apr 29, 2024
1 parent a6e2f45 commit 1df1203
Showing 1 changed file with 2 additions and 4 deletions.
6 changes: 2 additions & 4 deletions src/dbSta/src/dbReadVerilog.cc
Original file line number Diff line number Diff line change
Expand Up @@ -318,8 +318,7 @@ void Verilog2db::makeDbModule(
module = block_->getTopModule();
} else {
module = makeUniqueDbModule(network_->name(cell));
inst_module_vec.emplace_back(
std::pair<const Instance*, dbModule*>(inst, parent));
inst_module_vec.emplace_back(inst, parent);

std::string module_inst_name = network_->name(inst);
size_t last_idx = module_inst_name.find_last_of('/');
Expand Down Expand Up @@ -435,8 +434,7 @@ void Verilog2db::makeDbModule(
}
auto db_inst = dbInst::create(block_, master, child_name, false, module);

inst_module_vec.emplace_back(
std::pair<const Instance*, dbModule*>(child, module));
inst_module_vec.emplace_back(child, module);

if (db_inst == nullptr) {
logger_->warn(ORD,
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