Temporary stash of debug work, ignore. Signed-off-by: Andy Fox <andy…

…@rushc.com>

Signed-off-by: andyfox-rushc <[email protected]>

src/dbSta/src/dbNetwork.cc

@@ -43,6 +43,7 @@
 #include "sta/PortDirection.hh"
 #include "utl/Logger.h"
 
+
 namespace sta {
 
 using utl::ORD;
@@ -135,10 +136,47 @@ DbInstanceChildIterator::DbInstanceChildIterator(const Instance* instance,
   if (instance == network->topInstance() && block) {
     top_ = true;
     module_ = block -> getTopModule();
+
     dbSet<dbInst> insts = module_ -> getInsts();
     dbinst_iter_ = insts.begin();
     dbinst_iter_end_ = insts.end();
     top_ =true;
+
+    //compare the module instances iwth the block instances
+    int diff_count=0;
+    {
+      std::vector<dbInst*> module_insts;
+      for (auto i: module_ -> getInsts()){
+        module_insts.push_back(i);
+      }
+      std::vector<dbInst*> block_insts;
+      for (auto j: block -> getInsts()){
+        block_insts.push_back(j);
+      }
+
+      if (module_insts.size() != block_insts.size()){
+        printf("Module inst count %d block inst count %d\n",
+               module_insts.size(),
+               block_insts.size());
+        //       printf("%s Bad sized module/block",0x23);
+      }
+
+      for (int ix=0; ix < module_insts.size(); ix++){
+        if (module_insts.at(ix) -> getId() != block_insts.at(ix) -> getId()){
+          printf("Difference in block ix at %d Id %d not same as Id %d\n",
+                 ix,
+                 module_insts.at(ix) -> getId(),
+                 block_insts.at(ix) -> getId()
+                 );
+          diff_count++;
+        }
+      }
+      if (diff_count !=0){
+        printf(" Found diffs in block_insts and moudle_insts\n"/*,0x23*/);
+
+      }
+    }
+
     //original code
     /*
     dbSet<dbInst> insts = block->getInsts();    

src/dbSta/src/dbReadVerilog.cc

@@ -294,7 +294,8 @@ dbModule* Verilog2db::makeUniqueDbModule(const char* name)
 // Recursively builds odb's dbModule/dbModInst hierarchy corresponding
 // to the sta network rooted at inst.  parent is the dbModule to build
 // the hierarchy under. If null the top module is used.
-
+// If hierarchy_ is set to false, everything goes in the top level module
+
 void Verilog2db::makeDbModule(
     Instance* inst,
     dbModule* parent,
@@ -303,12 +304,12 @@ void Verilog2db::makeDbModule(
   Cell* cell = network_->cell(inst);
 
   dbModule* module;
-  if (parent == nullptr) {
+  if (parent == nullptr || hierarchy_ == false) {
     module = block_->getTopModule();
   } else {
+    //a hierarchical module
     module = makeUniqueDbModule(network_->name(cell));
     inst_module_vec.emplace_back(inst, parent);
-
     std::string module_inst_name = network_->name(inst);
     size_t last_idx = module_inst_name.find_last_of('/');
     if (last_idx != string::npos) {
@@ -391,9 +392,21 @@ void Verilog2db::makeDbModule(
       }
     }
   }
+
+
+  //reverse the list of instance creation when inserting in a module
+  //This assures order in modules matches order in dbVector
+  std::vector<Instance*> reversed_list;
   InstanceChildIterator* child_iter = network_->childIterator(inst);
   while (child_iter->hasNext()) {
     Instance* child = child_iter->next();
+    reversed_list.push_back(child);
+  }
+
+  for (std::vector<Instance*>::reverse_iterator rit = reversed_list.rbegin();
+       rit != reversed_list.rend();
+       ++rit){
+    Instance* child = *rit;
     if (network_->isHierarchical(child)) {
       makeDbModule(child, module, inst_module_vec);
     } else {
@@ -420,6 +433,10 @@ void Verilog2db::makeDbModule(
                       network_->name(cell));
         continue;
       }
+      //if we are in non-hierachical mode force everything into top module
+      if (hierarchy_ == false){
+        module =block_->getTopModule();
+      }
       auto db_inst = dbInst::create(block_, master, child_name, false, module);
 
       inst_module_vec.emplace_back(child, module);
@@ -432,10 +449,17 @@ void Verilog2db::makeDbModule(
                       module->getName());
         continue;
       }
+      if (hierarchy_==false){
+        module = block_->getTopModule();
+      }
+      //if we are in non-hierachical mode force everything into top module      
       module->addInst(db_inst);
     }
   }
-  delete child_iter;
+
+  if (hierarchy_==false)
+    module = block_->getTopModule();
+
   if (module->getChildren().reversible()
       && module->getChildren().orderReversed()) {
     module->getChildren().reverse();