Merge branch 'The-OpenROAD-Project:master' into vhier

andyfox-rushc · Jan 5, 2024 · 635a8f4 · 635a8f4
2 parents 2656293 + bc45157
commit 635a8f4
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diff --git a/src/pad/README.md b/src/pad/README.md
@@ -17,13 +17,16 @@ In the case where the bond pads are integrated into the padcell, the IO terminal
 To place a terminals on the padring
 
 ```tcl
-place_io_terminals inst_pins
+place_io_terminals
+    -allow_non_top_layer
+    inst_pins
 ```
 
 #### Options
 
 | Switch Name | Description |
 | ----- | ----- |
+| `-allow_non_top_layer` | Allow the terminal to be placed below the top layer. |
 | `inst_pins` | Instance pins to place the terminals on. |
 
 #### Examples

diff --git a/src/pad/include/pad/ICeWall.h b/src/pad/include/pad/ICeWall.h
@@ -122,7 +122,8 @@ class ICeWall
                      const odb::dbOrientType& rotation = odb::dbOrientType::R0,
                      const odb::Point& offset = {0, 0},
                      const std::string& prefix = "IO_BOND_");
-  void placeTerminals(const std::vector<odb::dbITerm*>& iterms);
+  void placeTerminals(const std::vector<odb::dbITerm*>& iterms,
+                      bool allow_non_top_layer);
   void routeRDL(odb::dbTechLayer* layer,
                 odb::dbTechVia* bump_via,
                 odb::dbTechVia* pad_via,

diff --git a/src/pad/src/ICeWall.cpp b/src/pad/src/ICeWall.cpp
@@ -989,7 +989,8 @@ void ICeWall::placeBondPads(odb::dbMaster* bond,
   }
 }
 
-void ICeWall::placeTerminals(const std::vector<odb::dbITerm*>& iterms)
+void ICeWall::placeTerminals(const std::vector<odb::dbITerm*>& iterms,
+                             const bool allow_non_top_layer)
 {
   auto* block = getBlock();
   if (block == nullptr) {
@@ -1045,10 +1046,19 @@ void ICeWall::placeTerminals(const std::vector<odb::dbITerm*>& iterms)
                      mterm->getName());
     }
 
+    auto layer = tech->findRoutingLayer(highest_level);
+    if (!allow_non_top_layer && layer != top_layer) {
+      logger_->error(utl::PAD,
+                     120,
+                     "No shape in terminal {}/{} found on layer {}",
+                     inst->getName(),
+                     mterm->getName(),
+                     top_layer->getName());
+    }
+
     odb::Rect shape = pin_shape->getBox();
     pad_transform.apply(shape);
 
-    auto layer = tech->findRoutingLayer(highest_level);
     makeBTerm(net, layer, shape);
   }
 }

diff --git a/src/pad/src/pad.i b/src/pad/src/pad.i
@@ -128,9 +128,10 @@ void place_bondpads(odb::dbMaster* master, const std::vector<odb::dbInst*>& pads
   ord::getICeWall()->placeBondPads(master, pads, rotation, {x_offset, y_offset}, prefix);
 }
 
-void place_terminals(const std::vector<odb::dbITerm*>& iterms)
+void place_terminals(const std::vector<odb::dbITerm*>& iterms,
+                     const bool allow_non_top_layer)
 {
-  ord::getICeWall()->placeTerminals(iterms);
+  ord::getICeWall()->placeTerminals(iterms, allow_non_top_layer);
 }
 
 void connect_by_abutment()

diff --git a/src/pad/src/pad.tcl b/src/pad/src/pad.tcl
@@ -334,16 +334,16 @@ proc place_bondpad {args} {
 sta::define_cmd_args "place_io_terminals" {inst_terms}
 
 proc place_io_terminals {args} {
-  sta::parse_key_args "place_bondpad" args \
+  sta::parse_key_args "place_io_terminals" args \
     keys {} \
-    flags {}
+    flags {-allow_non_top_layer}
 
   set iterms []
   foreach pin [get_pins {*}$args] {
     lappend iterms [ sta::sta_to_db_pin $pin]
   }
 
-  pad::place_terminals $iterms
+  pad::place_terminals $iterms [info exists flags(-allow_non_top_layer)]
 }
 
 sta::define_hidden_cmd_args "make_fake_io_site" {-name name \

diff --git a/src/pad/test/non_top_layer.def b/src/pad/test/non_top_layer.def
@@ -0,0 +1,16 @@
+VERSION 5.8 ;
+DIVIDERCHAR "/" ;
+BUSBITCHARS "[]" ;
+DESIGN soc_bsg_black_parrot ;
+UNITS DISTANCE MICRONS 2000 ;
+DIEAREA ( 0 0 ) ( 6000000 6000000 ) ;
+COMPONENTS 1 ;
+    - u_ci2_0_o PADCELL_SIG_V + FIXED ( 2660 2800 ) N ;
+END COMPONENTS
+PINS 1 ;
+    - p_ci2_0_o + NET p_ci2_0_o + DIRECTION OUTPUT + USE SIGNAL ;
+END PINS
+NETS 1 ;
+    - p_ci2_0_o ( PIN p_ci2_0_o ) ( u_ci2_0_o PAD ) + USE SIGNAL ;
+END NETS
+END DESIGN
diff --git a/src/pad/test/non_top_layer.lef b/src/pad/test/non_top_layer.lef
@@ -0,0 +1,174 @@
+VERSION 5.8 ;
+
+#NAMESCASESENSITIVE ON ;
+USEMINSPACING OBS OFF ;
+#BUSBITCHARS "[]" ;
+
+# UNITS
+# YBASE MICRON 1000 ;
+# END UNITS
+
+SITE IOSITE
+  SYMMETRY Y ;
+  CLASS PAD ;
+  SIZE    1.000 BY 140.000 ;
+END IOSITE
+
+# IO pad with no top level pin shape
+MACRO PADCELL_SIG_V
+  CLASS PAD AREAIO ;
+  ORIGIN 0 0 ;
+  FOREIGN PADCELL_SIG_V 0 0 ;
+  SIZE 25.0 BY 140 ;
+  SYMMETRY X Y R90 ;
+  SITE IOSITE ;
+  PIN PAD 
+    USE SIGNAL ;
+    DIRECTION INOUT ;
+    PORT
+      CLASS BUMP ;
+      LAYER metal9 ;
+        RECT 10.0 50.0 20.0 55.0 ;
+    END
+  END PAD
+  PIN A
+    USE SIGNAL ;
+    DIRECTION INPUT ;
+    PORT
+      CLASS CORE ;
+      LAYER metal4 ;
+        RECT 13.170 139.900 13.330 140.000 ;
+      LAYER metal5 ; 
+        RECT 13.170 139.900 13.330 140.000 ;
+      LAYER metal6 ; 
+        RECT 13.170 139.900 13.330 140.000 ;
+      LAYER metal7 ; 
+        RECT 13.170 139.900 13.330 140.000 ;
+      LAYER metal8 ;
+        RECT 13.170 139.900 13.330 140.000 ;
+      LAYER metal9 ;
+        RECT 13.170 139.900 13.330 140.000 ;
+    END
+  END A
+  PIN Y
+    USE SIGNAL ;
+    DIRECTION OUTPUT ;
+    PORT
+      CLASS CORE ;
+      LAYER metal4 ;
+        RECT 28.936 139.900 29.096 140.000 ;
+      LAYER metal5 ;
+        RECT 28.936 139.900 29.096 140.000 ;
+      LAYER metal6 ;
+        RECT 28.936 139.900 29.096 140.000 ;
+      LAYER metal7 ;
+        RECT 28.936 139.900 29.096 140.000 ;
+      LAYER metal8 ;
+        RECT 28.936 139.900 29.096 140.000 ;
+      LAYER metal9 ;
+        RECT 28.936 139.900 29.096 140.000 ;
+    END
+  END Y
+  PIN PU
+    USE SIGNAL ;
+    DIRECTION OUTPUT ;
+    PORT
+      CLASS CORE ;
+      LAYER metal4 ;
+        RECT 15.170 139.900 15.330 140.000 ;
+      LAYER metal5 ;
+        RECT 15.170 139.900 15.330 140.000 ;
+      LAYER metal6 ;
+        RECT 15.170 139.900 15.330 140.000 ;
+      LAYER metal7 ;
+        RECT 15.170 139.900 15.330 140.000 ;
+      LAYER metal8 ;
+        RECT 15.170 139.900 15.330 140.000 ;
+      LAYER metal9 ;
+        RECT 15.170 139.900 15.330 140.000 ;
+    END
+  END PU
+  PIN OE
+    USE SIGNAL ;
+    DIRECTION OUTPUT ;
+    PORT
+      CLASS CORE ;
+      LAYER metal4 ;
+        RECT 15.170 139.900 15.330 140.000 ;
+      LAYER metal5 ;
+        RECT 15.170 139.900 15.330 140.000 ;
+      LAYER metal6 ;
+        RECT 15.170 139.900 15.330 140.000 ;
+      LAYER metal7 ;
+        RECT 15.170 139.900 15.330 140.000 ;
+      LAYER metal8 ;
+        RECT 15.170 139.900 15.330 140.000 ;
+      LAYER metal9 ;
+        RECT 15.170 139.900 15.330 140.000 ;
+    END
+  END OE
+  PIN RETN
+    USE SIGNAL ;
+    DIRECTION INPUT ;
+    SHAPE ABUTMENT ;
+    PORT 
+      LAYER metal4 ;
+        RECT  0.000  99.900  0.100 100.00 ;
+      LAYER metal4 ;
+        RECT 24.900  99.900 25.000 100.00 ;
+    END
+  END RETN
+  PIN SNS
+    USE SIGNAL ;
+    DIRECTION INPUT ;
+    SHAPE ABUTMENT ;
+    PORT 
+      LAYER metal4 ;
+        RECT  0.000  89.900  0.100 90.00 ;
+      LAYER metal4 ;
+        RECT 24.900  89.900 25.000 90.00 ;
+    END
+  END SNS
+  PIN VDD
+    USE POWER ;
+    PORT
+      CLASS CORE ;
+      LAYER metal4 ;
+      RECT 0.000 20.0 0.100 21.0 ;
+      LAYER metal4 ;
+      RECT 24.90 20.0 25.00 21.0 ;
+    END
+  END VDD
+  PIN VSS
+    USE GROUND ;
+    PORT
+      CLASS CORE ;
+      LAYER metal4 ;
+      RECT 0.000 40.0 0.100 41.0 ;
+      LAYER metal4 ;
+      RECT 24.90 40.0 25.00 41.0 ;
+    END
+  END VSS
+  PIN DVDD
+    USE POWER ;
+    PORT
+      CLASS CORE ;
+      LAYER metal4 ;
+      RECT 0.000 60.0 0.100 61.0 ;
+      LAYER metal4 ;
+      RECT 24.90 60.0 25.00 61.0 ;
+    END
+  END DVDD
+  PIN DVSS
+    USE GROUND ;
+    PORT
+      CLASS CORE ;
+      LAYER metal4 ;
+      RECT 0.000 80.0 0.100 81.0 ;
+      LAYER metal4 ;
+      RECT 24.90 80.0 25.00 81.0 ;
+    END
+  END DVSS
+END PADCELL_SIG_V
+
+END LIBRARY
diff --git a/src/pad/test/non_top_layer.ok b/src/pad/test/non_top_layer.ok
@@ -0,0 +1,14 @@
+[INFO ODB-0222] Reading LEF file: Nangate45/Nangate45.lef
+[INFO ODB-0223]     Created 22 technology layers
+[INFO ODB-0224]     Created 27 technology vias
+[INFO ODB-0225]     Created 135 library cells
+[INFO ODB-0226] Finished LEF file:  Nangate45/Nangate45.lef
+[INFO ODB-0222] Reading LEF file: non_top_layer.lef
+[INFO ODB-0225]     Created 1 library cells
+[INFO ODB-0226] Finished LEF file:  non_top_layer.lef
+[INFO ODB-0128] Design: soc_bsg_black_parrot
+[INFO ODB-0130]     Created 1 pins.
+[INFO ODB-0131]     Created 1 components and 11 component-terminals.
+[INFO ODB-0133]     Created 1 nets and 1 connections.
+[INFO PAD-0116] Creating terminal for p_ci2_0_o on metal9 at (11.330um, 51.400um) - (21.330um, 56.400um)
+[ERROR PAD-0120] No shape in terminal u_ci2_0_o/PAD found on layer metal10
diff --git a/src/pad/test/non_top_layer.tcl b/src/pad/test/non_top_layer.tcl
@@ -0,0 +1,13 @@
+# Test for placing pads
+source "helpers.tcl"
+
+# Init chip
+read_lef Nangate45/Nangate45.lef
+
+# IO pad with no top level pin shape
+read_lef non_top_layer.lef
+
+read_def non_top_layer.def
+
+place_io_terminals -allow_non_top_layer */PAD
+catch {place_io_terminals */PAD}
diff --git a/src/pad/test/regression_tests.tcl b/src/pad/test/regression_tests.tcl
@@ -5,6 +5,7 @@ record_tests {
 
   make_corner_sites
   make_io_sites
+  non_top_layer
   place_pad
   place_pad_outsideofrow
   place_bondpad