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Merge pull request The-OpenROAD-Project#4607 from The-OpenROAD-Projec…
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…t-staging/secure-ins-delay2

phase 1 for enhanced insertion delay handling
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maliberty authored Feb 8, 2024
2 parents b090799 + a5f75fa commit 82bff87
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7 changes: 6 additions & 1 deletion src/cts/README.md
Original file line number Diff line number Diff line change
Expand Up @@ -52,6 +52,9 @@ clock_tree_synthesis
[-num_static_layers]
[-sink_clustering_buffer]
[-use_dummy_load]
[-insertion_delay]
[-sink_buffer_max_cap_derate derate_value]
[-delay_buffer_derate derate_value]
```

#### Options
Expand All @@ -75,8 +78,10 @@ clock_tree_synthesis
| `-sink_clustering_buffer` | Set the sink clustering buffer(s) to be used. |
| `-obstruction_aware` | Enables obstruction-aware buffering such that clock buffers are not placed on top of blockages or hard macros. This option may reduce legalizer displacement, leading to better latency, skew or timing QoR. The default value is `False`, and the allowed values are bool. |
| `-apply_ndr` | Applies 2X spacing non-default rule to all clock nets except leaf-level nets. The default value is `False`. |
| `-insertion_delay` | Considers insertion delays in macro timing models to improve clustering. The default value is `False`. |
| `-insertion_delay` | Considers insertion delays in macro timing models in balancing latencies between macro cells and registers. This option causes construction of separate clock trees for macro cells and registers. The default value is `False`. |
| `-use_dummy_load` | Applies dummy buffer or inverter cells at clock tree leaves to balance loads. The default values is `False`. |
| `-sink_buffer_max_cap_derate` | Use this option to control automatic buffer selection. To favor strong(weak) drive strength buffers use a small(large) value. The default value is `0.01`, meaning that buffers are selected by derating max cap limit by 0.01. The value of 1.0 means no derating of max cap limit. |
| `-delay_buffer_derate` | This option is used with -insertion_delay option that balances latencies between macro cells and registers by inserting delay buffers. The default values is `1.0`, meaning all needed delay buffers are inserted. Value of 0.5 means only half of necessary delay buffers are inserted. Value of 0.0 means no insertion of delay buffers. |

### Report CTS

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34 changes: 34 additions & 0 deletions src/cts/include/cts/TritonCTS.h
Original file line number Diff line number Diff line change
Expand Up @@ -54,6 +54,7 @@ class dbNet;
class dbITerm;
class dbMTerm;
class Rect;
class dbMaster;
} // namespace odb

namespace rsz {
Expand Down Expand Up @@ -83,6 +84,7 @@ class StaEngine;
class TreeBuilder;
class Clock;
class ClockSubNet;
class HTreeBuilder;

class TritonCTS
{
Expand Down Expand Up @@ -143,6 +145,28 @@ class TritonCTS
void disconnectAllPinsFromNet(odb::dbNet* net);
void checkUpstreamConnections(odb::dbNet* net);
void createClockBuffers(Clock& clockNet);
HTreeBuilder* initClockTreeForMacrosAndRegs(
odb::dbNet*& net,
const std::unordered_set<odb::dbMaster*>& buffer_masters,
Clock& ClockNet,
TreeBuilder* parentBuilder);
bool separateMacroRegSinks(
odb::dbNet*& net,
Clock& clockNet,
const std::unordered_set<odb::dbMaster*>& buffer_masters,
std::vector<std::pair<odb::dbInst*, odb::dbMTerm*>>& registerSinks,
std::vector<std::pair<odb::dbInst*, odb::dbMTerm*>>& macroSinks);
HTreeBuilder* addClockSinks(
Clock& clockNet,
odb::dbNet* physicalNet,
const std::vector<std::pair<odb::dbInst*, odb::dbMTerm*>>& sinks,
HTreeBuilder* parentBuilder,
const std::string& macrosOrRegs);
Clock forkRegisterClockNetwork(
Clock& clockNet,
const std::vector<std::pair<odb::dbInst*, odb::dbMTerm*>>& registerSinks,
odb::dbNet*& firstNet,
odb::dbNet*& secondNet);
void computeITermPosition(odb::dbITerm* term, int& x, int& y) const;
void countSinksPostDbWrite(TreeBuilder* builder,
odb::dbNet* net,
Expand All @@ -164,6 +188,7 @@ class TritonCTS
float getInputPinCap(odb::dbITerm* iterm);
bool isSink(odb::dbITerm* iterm);
ClockInst* getClockFromInst(odb::dbInst* inst);
bool hasInsertionDelay(odb::dbInst* inst, odb::dbMTerm* mterm);
double computeInsertionDelay(const std::string& name,
odb::dbInst* inst,
odb::dbMTerm* mterm);
Expand All @@ -182,6 +207,15 @@ class TritonCTS
ClockSubNet& subNet,
ClockInst& dummyClock);
void printClockNetwork(const Clock& clockNet) const;
void balanceMacroRegisterLatencies();
void computeAveSinkArrivals(TreeBuilder* builder);
void adjustLatencies(TreeBuilder* macroBuilder, TreeBuilder* registerBuilder);
void computeTopBufferDelay(TreeBuilder* builder);
odb::dbInst* insertDelayBuffer(odb::dbInst* driver,
int index,
const std::string& clockName,
int locX,
int locY);

sta::dbSta* openSta_;
sta::dbNetwork* network_;
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1 change: 1 addition & 0 deletions src/cts/src/Clock.h
Original file line number Diff line number Diff line change
Expand Up @@ -243,6 +243,7 @@ class Clock
}

std::string getName() const { return netName_; }
std::string getSdcName() const { return sdcClockName_; }
unsigned getNumSinks() const { return sinks_.size(); }

Box<int> computeSinkRegion();
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3 changes: 3 additions & 0 deletions src/cts/src/CtsOptions.h
Original file line number Diff line number Diff line change
Expand Up @@ -242,6 +242,8 @@ class CtsOptions
{
return sinkBufferMaxCapDerateSet_;
}
void setDelayBufferDerate(float derate) { delayBufferDerate_ = derate; }
float getDelayBufferDerate() const { return delayBufferDerate_; }
void enableDummyLoad(bool dummyLoad) { dummyLoad_ = dummyLoad; }
bool dummyLoadEnabled() const { return dummyLoad_; }

Expand Down Expand Up @@ -300,6 +302,7 @@ class CtsOptions
float sinkBufferMaxCapDerateDefault_ = 0.01;
float sinkBufferMaxCapDerate_ = sinkBufferMaxCapDerateDefault_;
bool dummyLoad_ = false;
float delayBufferDerate_ = 1.0; // no derate
};

} // namespace cts
19 changes: 19 additions & 0 deletions src/cts/src/TreeBuilder.h
Original file line number Diff line number Diff line change
Expand Up @@ -73,6 +73,13 @@ struct pointEqual
}
};

enum TreeType
{
regularTree = 0, // regular tree that drives both macros and registers
macroTree = 1, // parent tree that drives only macro cells with ins delays
registerTree = 2 // child tree that drives only registers without ins delays
};

class TreeBuilder
{
public:
Expand Down Expand Up @@ -219,6 +226,14 @@ class TreeBuilder
return x.computeDist(y) + getSinkInsertionDelay(x)
+ getSinkInsertionDelay(y);
}
TreeType getTreeType() const { return type_; }
void setTreeType(TreeType type) { type_ = type; }
float getAveSinkArrival() const { return aveArrival_; }
void setAveSinkArrival(float arrival) { aveArrival_ = arrival; }
float getTopBufferDelay() const { return topBufferDelay_; }
void setTopBufferDelay(float delay) { topBufferDelay_ = delay; }
odb::dbInst* getTopBuffer() const { return topBuffer_; }
void setTopBuffer(odb::dbInst* inst) { topBuffer_ = inst; }

protected:
CtsOptions* options_ = nullptr;
Expand All @@ -244,6 +259,10 @@ class TreeBuilder
// keep track of insertion delays at sink pins
boost::unordered_map<Point<double>, double, pointHash, pointEqual>
insertionDelays_;
TreeType type_ = regularTree;
float aveArrival_ = 0.0;
float topBufferDelay_ = 0.0;
odb::dbInst* topBuffer_ = nullptr;
};

} // namespace cts
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