test cases for pin swapping + 1st hierarhcical pin swap flow

Signed-off-by: andyfox-rushc <[email protected]>
andyfox-rushc · Nov 7, 2024 · 84167a4 · 84167a4
1 parent ac119a0
commit 84167a4
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Showing 8 changed files with 124 additions and 18 deletions.
diff --git a/src/dbSta/include/db_sta/dbNetwork.hh b/src/dbSta/include/db_sta/dbNetwork.hh
@@ -268,6 +268,7 @@ class dbNetwork : public ConcreteNetwork
 
   ////////////////////////////////////////////////////////////////
   // Port functions
+
   Cell* cell(const Port* port) const override;
   void registerConcretePort(const Port*);
 

diff --git a/src/dbSta/src/dbNetwork.cc b/src/dbSta/src/dbNetwork.cc
@@ -2011,6 +2011,22 @@ Pin* dbNetwork::connect(Instance* inst, Port* port, Net* net)
   }
   return pin;
 }
+/*
+bool dbNetwork::isDriver(const Pin* pin) const{
+  PortDirection *dir = direction(pin);
+  const Instance *inst = instance(pin);
+  odb::dbInst* db_inst;
+  odb::dbModInst* mod_inst;
+  staToDb(inst, db_inst, mod_inst);
+  if (isLeaf(inst) && dir->isAnyOutput()){
+    return true;
+  }
+  else if (mod_inst && dir->isAnyOutput()){
+    return true;
+  }
+  return false;
+}
+*/
 
 // Used by dbStaCbk
 // Incrementally update drivers.
@@ -2979,6 +2995,7 @@ void dbNetwork::hierarchicalConnect(dbITerm* source_pin,
       dbModITerm* mod_iterm
           = dbModITerm::create(parent_inst, connection_name_o.c_str());
       mod_iterm->setChildModBTerm(mod_bterm);
+      mod_bterm->setParentModITerm(mod_iterm);
       source_db_mod_net = dbModNet::create(cur_module, connection_name);
       mod_iterm->connect(source_db_mod_net);
       top_net = source_db_mod_net;

diff --git a/src/dbSta/src/dbReadVerilog.cc b/src/dbSta/src/dbReadVerilog.cc
@@ -453,6 +453,7 @@ void Verilog2db::makeDbModule(
         dbModule* module = modinst->getMaster();
         modbterm = module->findModBTerm(port_name_str.c_str());
         moditerm->setChildModBTerm(modbterm);
+        modbterm->setParentModITerm(moditerm);
 
         (void) moditerm;
         debugPrint(logger_,
@@ -644,9 +645,9 @@ void Verilog2db::makeDbNets(const Instance* inst)
   while (net_iter->hasNext()) {
     Net* net = net_iter->next();
     const char* net_name = network_->pathName(net);
+
     if (is_top || !hasTerminals(net)) {
       dbNet* db_net = dbNet::create(block_, net_name);
-
       if (network_->isPower(net)) {
         db_net->setSigType(odb::dbSigType::POWER);
       }
@@ -716,14 +717,38 @@ void Verilog2db::makeVModNets(const Instance* inst, dbModInst* mod_inst)
   std::unique_ptr<InstancePinIterator> pinIter{network_->pinIterator(inst)};
   while (pinIter->hasNext()) {
     Pin* inst_pin = pinIter->next();
-
     Net* inst_pin_net = network_->net(inst_pin);
+
     if (!inst_pin_net) {
       continue;
     }
 
     dbModNet* upper_mod_net = constructModNet(inst_pin_net, parent_module);
-    (void) upper_mod_net;
+
+    dbModITerm* mod_iterm = nullptr;
+    dbModBTerm* mod_bterm = nullptr;
+    dbBTerm* bterm = nullptr;
+    dbITerm* iterm = nullptr;
+    staToDb(child_module, inst_pin, bterm, iterm, mod_bterm, mod_iterm);
+    if (mod_bterm) {
+      mod_iterm = mod_bterm->getParentModITerm();
+      if (mod_iterm) {
+        mod_iterm->connect(upper_mod_net);
+      }
+    }
+
+    // make sure any top level bterms are connected to this net too...
+    if (parent_module == block_->getTopModule()) {
+      NetConnectedPinIterator* pin_iter
+          = network_->connectedPinIterator(inst_pin_net);
+      while (pin_iter->hasNext()) {
+        const Pin* pin = pin_iter->next();
+        staToDb(parent_module, pin, bterm, iterm, mod_bterm, mod_iterm);
+        if (bterm) {
+          bterm->connect(upper_mod_net);
+        }
+      }
+    }
 
     // push down inside the hierarchical instance to find any
     // modnets connected on the inside of the instance

diff --git a/src/rsz/src/RepairSetup.cc b/src/rsz/src/RepairSetup.cc
@@ -259,6 +259,9 @@ bool RepairSetup::repairSetup(const float setup_slack_margin,
         break;
       }
       PathRef end_path = sta_->vertexWorstSlackPath(end, max_);
+
+      Pin* end_pin = end->pin();
+
       const bool changed = repairPath(end_path,
                                       end_slack,
                                       skip_pin_swap,
@@ -1917,6 +1920,8 @@ void RepairSetup::repairSetupLastGasp(const OptoParams& params, int& num_viols)
         break;
       }
       PathRef end_path = sta_->vertexWorstSlackPath(end, max_);
+      Pin* end_pin = end->pin();
+
       const bool changed = repairPath(end_path,
                                       end_slack,
                                       true /* skip_pin_swap */,

diff --git a/src/rsz/src/Resizer.cc b/src/rsz/src/Resizer.cc
@@ -1231,36 +1231,70 @@ void Resizer::swapPins(Instance* inst,
   Pin *found_pin1, *found_pin2;
   Net *net1, *net2;
 
+  odb::dbModNet* mod_net_pin1 = nullptr;
+  odb::dbNet* flat_net_pin1 = nullptr;
+
+  odb::dbModNet* mod_net_pin2 = nullptr;
+  odb::dbNet* flat_net_pin2 = nullptr;
+
+  odb::dbITerm* iterm_pin1 = nullptr;
+  odb::dbITerm* iterm_pin2 = nullptr;
+
   InstancePinIterator* pin_iter = network_->pinIterator(inst);
   found_pin1 = found_pin2 = nullptr;
   net1 = net2 = nullptr;
   while (pin_iter->hasNext()) {
     Pin* pin = pin_iter->next();
     Net* net = network_->net(pin);
     LibertyPort* port = network_->libertyPort(pin);
+
     // port pointers may change after sizing
     // if (port == port1) {
     if (std::strcmp(port->name(), port1->name()) == 0) {
       found_pin1 = pin;
       net1 = net;
+      flat_net_pin1 = db_network_->flatNet(found_pin1);
+      mod_net_pin1 = db_network_->hierNet(found_pin1);
+      iterm_pin1 = db_network_->flatPin(found_pin1);
     }
     if (std::strcmp(port->name(), port2->name()) == 0) {
       found_pin2 = pin;
       net2 = net;
+      flat_net_pin2 = db_network_->flatNet(found_pin2);
+      mod_net_pin2 = db_network_->hierNet(found_pin2);
+      iterm_pin2 = db_network_->flatPin(found_pin2);
     }
   }
 
   if (net1 != nullptr && net2 != nullptr) {
     // Swap the ports and nets
+    // Support for hierarchy, swap modnets as well as dbnets
+
+    // disconnect everything connected to found_pin1
     sta_->disconnectPin(found_pin1);
-    sta_->connectPin(inst, port1, net2);
+    //  sta_->connectPin(inst, port1, net2);
+    if (flat_net_pin2) {
+      iterm_pin1->connect(flat_net_pin2);
+    }
+    if (mod_net_pin2) {
+      iterm_pin1->connect(mod_net_pin2);
+    }
+
     sta_->disconnectPin(found_pin2);
-    sta_->connectPin(inst, port2, net1);
+    // sta_->connectPin(inst, port2, net1);
+    if (flat_net_pin1) {
+      iterm_pin2->connect(flat_net_pin1);
+    }
+    if (mod_net_pin1) {
+      iterm_pin2->connect(mod_net_pin1);
+    }
 
     // Invalidate the parasitics on these two nets.
     if (haveEstimatedParasitics()) {
-      invalidateParasitics(found_pin2, net1);
-      invalidateParasitics(found_pin1, net2);
+      invalidateParasitics(found_pin2,
+                           db_network_->dbToSta(flat_net_pin1));  // net1);
+      invalidateParasitics(found_pin1,
+                           db_network_->dbToSta(flat_net_pin2));  // net2);
     }
   }
 }

diff --git a/src/rsz/test/pinswap_flat.tcl b/src/rsz/test/pinswap_flat.tcl
@@ -6,7 +6,18 @@ read_lef Nangate45/Nangate45.lef
 read_verilog pinswap_flat.v
 link_design td1
 
-read_sdc repair_setup2.sdc
+create_clock [get_ports clk] -period 0.1
+set_clock_uncertainty 0  [get_clocks clk]
+set_input_delay -clock clk  0.02  [get_ports a1]
+set_input_delay -clock clk  0.02  [get_ports a2]
+set_input_delay -clock clk  0.02  [get_ports a3]
+set_input_delay -clock clk  0.00  [get_ports a4]
+set_input_delay -clock clk  0.00  [get_ports a5]
+set_input_delay -clock clk  0.00  [get_ports a6]
+
+set_output_delay -clock clk  0.01  [get_ports y1]
+set_output_delay -clock clk  0.01  [get_ports y2]
+
 
 #place the design
 initialize_floorplan -die_area "0 0 40 1200"   -core_area "0 0 40 1200" -site FreePDK45_38x28_10R_NP_162NW_34O

diff --git a/src/rsz/test/pinswap_flat.v b/src/rsz/test/pinswap_flat.v
@@ -8,16 +8,17 @@ module td1 (a1,
     y1,
     y2);
 
- input a1;
- input a2;
- input a3;
- input a4;
- input a5;
- input a6;         
- input clk;
- output y1;
- output y2;
+   input clk;
+   output y1;
+   output y2;
 
+   input a1;
+   input a2;
+   input a3;
+   input a4;
+   input a5;
+   input a6;
+
  wire n1;
  wire net1;
  wire net2;

diff --git a/src/rsz/test/pinswap_hier.tcl b/src/rsz/test/pinswap_hier.tcl
@@ -7,7 +7,19 @@ read_lef Nangate45/Nangate45.lef
 read_verilog pinswap_hier.v
 link_design td1 -hier
 
-read_sdc repair_setup2.sdc
+create_clock [get_ports clk] -period 0.1
+set_clock_uncertainty 0  [get_clocks clk]
+set_input_delay -clock clk  0.02  [get_ports a1]
+set_input_delay -clock clk  0.02  [get_ports a2]
+set_input_delay -clock clk  0.02  [get_ports a3]
+set_input_delay -clock clk  0.00  [get_ports a4]
+set_input_delay -clock clk  0.00  [get_ports a5]
+set_input_delay -clock clk  0.00  [get_ports a6]
+
+set_output_delay -clock clk  0.01  [get_ports y1]
+set_output_delay -clock clk  0.01  [get_ports y2]
+
+
 
 #place the design
 initialize_floorplan -die_area "0 0 40 1200"   -core_area "0 0 40 1200" -site FreePDK45_38x28_10R_NP_162NW_34O