Added hierarchical tests for next pull request. Signed-off-by: Andy F…

…ox <[email protected]>

Signed-off-by: andyfox-rushc <[email protected]>

src/dbSta/test/hier2.ok

@@ -0,0 +1,5 @@
+[INFO ODB-0222] Reading LEF file: example1.lef
+[INFO ODB-0223]     Created 2 technology layers
+[INFO ODB-0225]     Created 6 library cells
+[INFO ODB-0226] Finished LEF file:  example1.lef
+No differences found.

src/dbSta/test/hier2.tcl

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+# hieararchical verilog
+source "helpers.tcl"
+read_lef example1.lef
+read_liberty example1_typ.lib
+read_verilog hier2.v
+link_design top
+write_verilog hier2_out.v
+diff_files hier2_out.v hier2_out.vok
+

src/dbSta/test/hier2.v

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+/*
+ lef: example1.lef
+ lib: example1_typ.lib
+ 
+ */
+
+module gate1 (a1,a2,zn);
+   input a1;
+   input a2;
+   output zn;
+
+   AND2_X1 _5_ (
+    .A1(a1),
+    .A2(a2),
+    .ZN(zn)
+  );
+
+endmodule // gatel
+
+module top (a,b, out);
+   input a;
+   input b;
+   output out;
+
+
+   wire   a_int;
+
+  INV_X1 _4_ (
+    .A(a),
+    .ZN(a_int)
+  );
+
+//   gate1 gate1_inst (
+//	      .a1(a_int),
+//	      .a2(b),
+//	      .zn(out)
+//	      );
+
+   gate1 gate2_inst (
+	      .a1(a_int),
+	      .a2(b),
+	      .zn(out)
+	      );
+
+
+
+endmodule

src/dbSta/test/hier2_out.vok

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+module top (a,
+    b,
+    out);
+ input a;
+ input b;
+ output out;
+
+ wire a_int;
+
+ INV_X1 _4_ (.ZN(a_int),
+    .A(a));
+ gate1 gate2_inst (.zn(out),
+    .a2(b),
+    .a1(a_int));
+endmodule
+module gate1 (zn,
+    a2,
+    a1);
+ output zn;
+ input a2;
+ input a1;
+
+
+ AND2_X1 \gate2_inst/_5_  (.ZN(zn),
+    .A1(a1),
+    .A2(a2));
+endmodule