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Hierarchical id encoding, test for clocks constrained on same port to…
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… show unique ids. Signed-off-by: Andy Fox <[email protected]>

Signed-off-by: andyfox-rushc <[email protected]>
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andyfox-rushc committed May 23, 2024
1 parent faa412e commit ce54e9d
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Showing 3 changed files with 481 additions and 23 deletions.
87 changes: 64 additions & 23 deletions src/dbSta/src/dbNetwork.cc
View file
Original file line number Diff line number Diff line change
Expand Up @@ -273,8 +273,12 @@ DbInstancePinIterator::DbInstancePinIterator(const Instance* inst,

if (top_) {
dbBlock* block = network->block();
bitr_ = block->getBTerms().begin();
bitr_end_ = block->getBTerms().end();
// it is possible that a block might not have been created if no design
// has been read in.
if (block) {
bitr_ = block->getBTerms().begin();
bitr_end_ = block->getBTerms().end();
}
} else {
dbInst* db_inst;
dbModInst* mod_inst;
Expand Down Expand Up @@ -427,9 +431,7 @@ DbNetTermIterator::DbNetTermIterator(const Net* net, const dbNetwork* network)

bool DbNetTermIterator::hasNext()
{
if (mod_iter_ != mod_end_ || iter_ != end_)
return true;
return false;
return (mod_iter_ != mod_end_ || iter_ != end_);
}

Term* DbNetTermIterator::next()
Expand Down Expand Up @@ -508,6 +510,17 @@ ObjectId dbNetwork::id(const Instance* instance) const
if (instance == top_instance_) {
return 0;
}
if (hierarchy_) {
dbInst* db_inst;
dbModInst* mod_inst;
staToDb(instance, db_inst, mod_inst);
if (db_inst) {
return db_inst->getId() >> 2;
}
if (mod_inst) {
return (mod_inst->getId() >> 2) + 1;
}
}
return staToDb(instance)->getId();
}

Expand Down Expand Up @@ -574,7 +587,6 @@ void dbNetwork::makeVerilogCell(Library* library, dbModInst* mod_inst)
}
}

// upto here.
Cell* dbNetwork::cell(const Instance* instance) const
{
if (instance == top_instance_) {
Expand Down Expand Up @@ -754,27 +766,44 @@ ObjectId dbNetwork::id(const Pin* pin) const
dbModITerm* moditerm = nullptr;
dbModBTerm* modbterm = nullptr;

staToDb(pin, iterm, bterm, moditerm, modbterm);
static std::map<ObjectId, void*> id_ptr_map;

if (iterm != nullptr) {
return iterm->getId() << 1;
}
if (bterm != nullptr) {
return (bterm->getId() << 1) + 1;
}
staToDb(pin, iterm, bterm, moditerm, modbterm);

if (moditerm != nullptr) {
return (moditerm->getId());
}
if (modbterm != nullptr) {
return (modbterm->getId());
if (hierarchy_) {
// The id is used by the STA traversers to accumulate visited.
// lower bits used to encode type
// id,00 <- iterm
// id,01 <- bterm
// id,10 <- moditerm
// id,11 <- modbterm
if (iterm != nullptr) {
return iterm->getId() << 2;
}
if (bterm != nullptr) {
return (bterm->getId() << 2) | 1;
}
if (moditerm != nullptr) {
return (moditerm->getId() << 2) | 2;
}
if (modbterm != nullptr) {
return (modbterm->getId() << 2) | 3;
}
} else {
if (iterm != nullptr) {
return iterm->getId() << 1;
}
if (bterm != nullptr) {
return (bterm->getId() << 1) + 1;
}
}
return 0;
}

Instance* dbNetwork::instance(const Pin* pin) const
{
dbITerm* iterm;

dbBTerm* bterm;
dbModITerm* moditerm = nullptr;
dbModBTerm* modbterm = nullptr;
Expand Down Expand Up @@ -814,9 +843,6 @@ Net* dbNetwork::net(const Pin* pin) const
// that we have both a mod net and a dbinst net.
// In the case of writing out a hierachical network we always
// choose the mnet.
if (dnet && mnet) {
return dbToSta(mnet);
}
if (mnet)
return dbToSta(mnet);
if (dnet)
Expand Down Expand Up @@ -937,7 +963,7 @@ PortDirection* dbNetwork::direction(const Pin* pin) const
// get the direction off the modbterm
std::string pin_name = moditerm->getName();
dbModInst* mod_inst = moditerm->getParent();
dbModule* module = mod_inst->getParent();
dbModule* module = mod_inst->getMaster();
dbModBTerm* modbterm_local = module->findModBTerm(pin_name.c_str());
PortDirection* dir
= dbToSta(modbterm_local->getSigType(), modbterm_local->getIoType());
Expand Down Expand Up @@ -969,6 +995,7 @@ void dbNetwork::setVertexId(Pin* pin, VertexId id)
dbModITerm* moditerm = nullptr;
dbModBTerm* modbterm = nullptr;
staToDb(pin, iterm, bterm, moditerm, modbterm);
// timing arcs only set on leaf level iterm/bterm.
if (iterm) {
iterm->staSetVertexId(id);
} else if (bterm) {
Expand Down Expand Up @@ -1041,7 +1068,20 @@ bool dbNetwork::isPlaced(const Pin* pin) const

ObjectId dbNetwork::id(const Net* net) const
{
return staToDb(net)->getId();
dbModNet* modnet = nullptr;
dbNet* dnet = nullptr;
staToDb(net, dnet, modnet);
if (hierarchy_) {
if (dnet) {
return dnet->getId() << 2;
}
if (modnet) {
return (modnet->getId() << 2) + 1;
}
} else {
return dnet->getId();
}
return 0;
}

const char* dbNetwork::name(const Net* net) const
Expand Down Expand Up @@ -1758,6 +1798,7 @@ void dbNetwork::staToDb(const Pin* pin,
dbITerm*& iterm,
dbBTerm*& bterm,
dbModITerm*& moditerm,
// axiom never see a modbterm...
dbModBTerm*& modbterm) const
{
iterm = nullptr;
Expand Down
70 changes: 70 additions & 0 deletions src/dbSta/test/hierclock.ok
View file
Original file line number Diff line number Diff line change
@@ -0,0 +1,70 @@
[INFO ODB-0227] LEF file: Nangate45/Nangate45.lef, created 22 layers, 27 vias, 135 library cells
Startpoint: U2/_66_ (rising edge-triggered flip-flop clocked by clk1)
Endpoint: U2/_66_ (rising edge-triggered flip-flop clocked by clk1)
Path Group: clk1
Path Type: min

Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 0.00 clock clk1 (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 0.00 ^ U2/_66_/CK (DFF_X1)
1 1.55 0.01 0.06 0.06 v U2/_66_/QN (DFF_X1)
_41_ (net)
0.01 0.00 0.06 v U2/_49_/A (INV_X1)
1 1.68 0.01 0.01 0.08 ^ U2/_49_/ZN (INV_X1)
_26_ (net)
0.01 0.00 0.08 ^ U2/_53_/B2 (AOI21_X1)
1 1.06 0.01 0.01 0.09 v U2/_53_/ZN (AOI21_X1)
_13_ (net)
0.01 0.00 0.09 v U2/_66_/D (DFF_X1)
0.09 data arrival time

0.00 0.00 0.00 clock clk1 (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 clock reconvergence pessimism
0.00 ^ U2/_66_/CK (DFF_X1)
0.00 0.00 library hold time
0.00 data required time
-----------------------------------------------------------------------------
0.00 data required time
-0.09 data arrival time
-----------------------------------------------------------------------------
0.09 slack (MET)


Startpoint: U3/_66_ (rising edge-triggered flip-flop clocked by clk2)
Endpoint: U3/_66_ (rising edge-triggered flip-flop clocked by clk2)
Path Group: clk2
Path Type: min

Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 0.00 clock clk2 (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 0.00 ^ U3/_66_/CK (DFF_X1)
1 1.55 0.01 0.06 0.06 v U3/_66_/QN (DFF_X1)
_41_ (net)
0.01 0.00 0.06 v U3/_49_/A (INV_X1)
1 1.68 0.01 0.01 0.08 ^ U3/_49_/ZN (INV_X1)
_26_ (net)
0.01 0.00 0.08 ^ U3/_53_/B2 (AOI21_X1)
1 1.06 0.01 0.01 0.09 v U3/_53_/ZN (AOI21_X1)
_13_ (net)
0.01 0.00 0.09 v U3/_66_/D (DFF_X1)
0.09 data arrival time

0.00 0.00 0.00 clock clk2 (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 clock reconvergence pessimism
0.00 ^ U3/_66_/CK (DFF_X1)
0.00 0.00 library hold time
0.00 data required time
-----------------------------------------------------------------------------
0.00 data required time
-0.09 data arrival time
-----------------------------------------------------------------------------
0.09 slack (MET)


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