updated from master

Signed-off-by: andyfox-rushc <[email protected]>

.github/workflows/github-actions-clang-tidy.yml

@@ -17,6 +17,7 @@ jobs:
           build_dir: './build'
           cmake_command: cmake . -B build
           config_file: '.clang-tidy'
+          exclude: "*/codeGenerator/templates/*"
           split_workflow: true
       - name: Upload Artifacts
         uses: actions/upload-artifact@v3

etc/CodeCoverage.sh

@@ -16,6 +16,8 @@ EOF
 _lcov() {
     ./test/regression
 
+    # sta has a private test suite; mpl is obsoleted by mpl2;
+    # drt's gr is not in use
     mkdir -p coverage-output
     lcov \
         --capture \
@@ -27,6 +29,10 @@ _lcov() {
         --exclude "*/.local/*" \
         --exclude "*build*" \
         --exclude "*/third-party/*" \
+        --exclude "*/sta/*" \
+        --exclude "*/mpl/*" \
+        --exclude "*/drt/src/gr/*" \
+        --exclude "*/drt/src/db/grObj/*" \
         --output-file ./coverage-output/main_coverage.info
 
     genhtml ./coverage-output/main_coverage.info \

etc/DependencyInstaller.sh

@@ -14,7 +14,7 @@ _equivalenceDeps() {
 
     # yosys
     yosysPrefix=${PREFIX:-"/usr/local"}
-    if ! command -v yosys &> /dev/null; then (
+    if [[ ! $(command -v yosys) || ! $(command -v yosys-config)  ]]; then (
         if [[ -f /opt/rh/llvm-toolset-7.0/enable ]]; then
             source /opt/rh/llvm-toolset-7.0/enable
         fi

include/ord/Design.h

@@ -41,6 +41,7 @@
 
 namespace odb {
 class dbBlock;
+class dbDatabase;
 class dbMaster;
 class dbMTerm;
 class dbNet;
@@ -192,6 +193,14 @@ class Design
   pdn::PdnGen* getPdnGen();
   pad::ICeWall* getICeWall();
 
+  // This returns a database that is not the one associated with
+  // the rest of the application.  It is usable as a standalone
+  // db but should not passed to any other Design or Tech APIs.
+  //
+  // This is useful if you need a second database for specialized
+  // use cases and is not ordinarily required.
+  static odb::dbDatabase* createDetachedDb();
+
  private:
   sta::dbSta* getSta();
   sta::LibertyCell* getLibertyCell(odb::dbMaster* master);

src/CMakeLists.txt

@@ -166,7 +166,7 @@ if (BUILD_TCLX AND TCLX_H)
   message(STATUS "TclX header: ${TCLX_H}")
 endif()
 
-find_package(SWIG 3.0 REQUIRED)
+find_package(SWIG 4.0 REQUIRED)
 if (SWIG_VERSION VERSION_GREATER_EQUAL "4.1.0")
   message(STATUS "Using SWIG >= ${SWIG_VERSION} -flatstaticmethod flag for python")
 endif()

src/Design.cc

@@ -347,4 +347,13 @@ pad::ICeWall* Design::getICeWall()
   return app->getICeWall();
 }
 
+/* static */
+odb::dbDatabase* Design::createDetachedDb()
+{
+  auto app = OpenRoad::openRoad();
+  auto db = odb::dbDatabase::create();
+  db->setLogger(app->getLogger());
+  return db;
+}
+
 }  // namespace ord

src/OpenRoad.tcl

@@ -395,5 +395,34 @@ proc get_core_area { } {
   return $area
 }
 
+proc parse_list_args {cmd arg_var list_var lists_args} {
+  upvar 1 $arg_var args
+  upvar 1 $list_var list
+
+  foreach arg_opt $lists_args {
+    set remaining_args []
+
+    set list($arg_opt) []
+    for {set i 0} {$i < [llength $args]} {incr i} {
+      set arg [lindex $args $i]
+      if { [sta::is_keyword_arg $arg] } {
+        if { $arg == $arg_opt } {
+          incr i
+          if { [llength $args] == $i } {
+            utl::error ORD 560 "$cmd $arg_opt missing value."
+          }
+          lappend list($arg_opt) [lindex $args $i]
+        } else {
+          lappend remaining_args $arg
+        }
+      } else {
+        lappend remaining_args $arg
+      }
+    }
+
+    set args $remaining_args
+  }
+}
+
 # namespace ord
 }

src/cts/src/TechChar.cpp

@@ -601,8 +601,12 @@ void TechChar::initCharacterization()
       sta::LibertyLibrary* lib = libertyCell->libertyLibrary();
 
       output->slewLimit(sta::MinMax::max(), maxSlew, maxSlewExist);
-      if (!maxSlewExist)
+      if (!maxSlewExist) {
+        input->slewLimit(sta::MinMax::max(), maxSlew, maxSlewExist);
+      }
+      if (!maxSlewExist) {
         lib->defaultMaxSlew(maxSlew, maxSlewExist);
+      }
       if (!maxSlewExist)
         logger_->error(
             CTS, 107, "No max slew found for cell {}.", bufMasterName);

src/cts/test/array.ok

@@ -82,11 +82,11 @@ legalized HPWL         133357.9 u
 delta HPWL                    0 %
 
 Clock clk
-Latency      CRPR       Skew
-inst_7_12/clk ^
-   1.27
-inst_8_12/clk ^
-   1.14      0.00       0.13
+   1.27 source latency inst_7_12/clk ^
+  -1.14 target latency inst_8_12/clk ^
+   0.00 CRPR
+--------------
+   0.13 setup skew
 
 Startpoint: inst_1_1 (rising edge-triggered flip-flop clocked by clk)
 Endpoint: inst_2_1 (rising edge-triggered flip-flop clocked by clk)

src/cts/test/array_ins_delay.ok

@@ -133,11 +133,13 @@ legalized HPWL         186297.4 u
 delta HPWL                    0 %
 
 Clock clk
-Latency      CRPR       Skew
-inst_7_9/clk ^
-   1.30
-inst_8_9/clk ^
-   1.13      0.00       0.17
+   1.30 source latency inst_7_9/clk ^
+   0.00 source clock tree delay
+  -1.13 target latency inst_8_9/clk ^
+  -0.00 target clock tree delay
+   0.00 CRPR
+--------------
+   0.17 setup skew
 
 Startpoint: inst_1_1 (rising edge-triggered flip-flop clocked by clk)
 Endpoint: inst_2_1 (rising edge-triggered flip-flop clocked by clk)

src/cts/test/array_no_blockages.ok

@@ -82,9 +82,9 @@ legalized HPWL         133583.9 u
 delta HPWL                    0 %
 
 Clock clk
-Latency      CRPR       Skew
-inst_8_14/clk ^
-   1.24
-inst_10_14/clk ^
-   1.10      0.00       0.14
+   1.24 source latency inst_8_14/clk ^
+  -1.10 target latency inst_10_14/clk ^
+   0.00 CRPR
+--------------
+   0.14 setup skew
 

src/dbSta/src/dbSta.cc

@@ -354,7 +354,7 @@ std::string dbSta::getInstanceTypeText(InstType type)
     case STD_PHYSICAL:
       return "Generic Physical";
     case STD_COMBINATIONAL:
-      return "Complex combinational cell";
+      return "Multi-Input combinational cell";
     case STD_OTHER:
       return "Other";
   }
@@ -479,12 +479,14 @@ std::map<dbSta::InstType, int> dbSta::countInstancesByType()
 void dbSta::report_cell_usage()
 {
   std::map<InstType, int> instances_types = countInstancesByType();
+  int total_usage = db_->getChip()->getBlock()->getInsts().size();
 
   logger_->report("Cell usage report:");
   for (auto [type, count] : instances_types) {
     std::string type_name = getInstanceTypeText(type);
     logger_->report("  {}s: {}", type_name, count);
   }
+  logger_->report("  Total: {}", total_usage);
 }
 
 

src/dbSta/test/report_cell_usage.ok

@@ -11,4 +11,5 @@ Cell usage report:
   Fill cells: 168
   Buffer/inverters: 232
   Sequential cells: 35
-  Complex combinational cells: 241
+  Multi-Input combinational cells: 241
+  Total: 676

src/grt/src/GlobalRouter.cpp

@@ -2476,8 +2476,8 @@ void GlobalRouter::initGrid(int max_layer)
 
   int tile_size = grid_->getPitchesInTile() * track_spacing;
 
-  int x_grids = upper_rightX / tile_size;
-  int y_grids = upper_rightY / tile_size;
+  int x_grids = std::max(1, upper_rightX / tile_size);
+  int y_grids = std::max(1, upper_rightY / tile_size);
 
   bool perfect_regular_x = (x_grids * tile_size) == upper_rightX;
   bool perfect_regular_y = (y_grids * tile_size) == upper_rightY;
@@ -3406,7 +3406,10 @@ void GlobalRouter::getBlockage(odb::dbTechLayer* layer,
                                uint8_t& blockage_h,
                                uint8_t& blockage_v)
 {
-  fastroute_->getBlockage(layer, x, y, blockage_h, blockage_v);
+  int max_layer = std::max(max_routing_layer_, max_layer_for_clock_);
+  if (layer->getRoutingLevel() <= max_layer) {
+    fastroute_->getBlockage(layer, x, y, blockage_h, blockage_v);
+  }
 }
 
 std::map<int, odb::dbTechVia*> GlobalRouter::getDefaultVias(

src/grt/test/regression_tests.tcl

@@ -53,6 +53,7 @@ record_tests {
   report_wire_length6
   set_nets_to_route1
   silence
+  single_row
   top_level_term1
   top_level_term2
   top_level_term3

src/grt/test/single_row.def

@@ -0,0 +1,31 @@
+VERSION 5.8 ;
+DIVIDERCHAR "/" ;
+BUSBITCHARS "[]" ;
+DESIGN single_row ;
+UNITS DISTANCE MICRONS 1000 ;
+DIEAREA ( 0 0 ) ( 5760 3330 ) ;
+ROW ROW_0 unit 0 0 N DO 4 BY 1 STEP 480 0 ;
+TRACKS X 240 DO 12 STEP 480 LAYER li1 ;
+TRACKS Y 185 DO 9 STEP 370 LAYER li1 ;
+TRACKS X 185 DO 15 STEP 370 LAYER met1 ;
+TRACKS Y 185 DO 9 STEP 370 LAYER met1 ;
+GCELLGRID X 0 DO 1 STEP 5550 ;
+GCELLGRID Y 0 DO 1 STEP 5550 ;
+COMPONENTS 1 ;
+    - buffer sky130_fd_sc_hs__buf_1 + PLACED ( 1920 0 ) N ;
+END COMPONENTS
+PINS 2 ;
+    - a_i + NET a_i + DIRECTION INPUT + USE SIGNAL
+      + PORT
+        + LAYER li1 ( -85 -165 ) ( 85 165 )
+        + PLACED ( 2160 165 ) N ;
+    - b_o + NET b_o + DIRECTION OUTPUT + USE SIGNAL
+      + PORT
+        + LAYER li1 ( -85 -165 ) ( 85 165 )
+        + PLACED ( 4080 3165 ) N ;
+END PINS
+NETS 2 ;
+    - a_i ( PIN a_i ) ( buffer A ) + USE SIGNAL ;
+    - b_o ( PIN b_o ) ( buffer X ) + USE SIGNAL ;
+END NETS
+END DESIGN

src/grt/test/single_row.guideok

@@ -0,0 +1,10 @@
+a_i
+(
+0 0 5760 3330 li1
+0 0 5760 3330 met1
+)
+b_o
+(
+0 0 5760 3330 li1
+0 0 5760 3330 met1
+)

src/grt/test/single_row.ok

@@ -0,0 +1,46 @@
+[INFO ODB-0222] Reading LEF file: sky130hs/sky130hs.tlef
+[INFO ODB-0223]     Created 13 technology layers
+[INFO ODB-0224]     Created 25 technology vias
+[INFO ODB-0226] Finished LEF file:  sky130hs/sky130hs.tlef
+[INFO ODB-0222] Reading LEF file: sky130hs/sky130hs_std_cell.lef
+[INFO ODB-0225]     Created 390 library cells
+[INFO ODB-0226] Finished LEF file:  sky130hs/sky130hs_std_cell.lef
+[INFO ODB-0128] Design: single_row
+[INFO ODB-0130]     Created 2 pins.
+[INFO ODB-0131]     Created 1 components and 6 component-terminals.
+[INFO ODB-0133]     Created 2 nets and 2 connections.
+[INFO GRT-0020] Min routing layer: li1
+[INFO GRT-0021] Max routing layer: met1
+[INFO GRT-0022] Global adjustment: 0%
+[INFO GRT-0023] Grid origin: (0, 0)
+[INFO GRT-0043] No OR_DEFAULT vias defined.
+[INFO GRT-0088] Layer li1     Track-Pitch = 0.4800  line-2-Via Pitch: 0.3400
+[INFO GRT-0088] Layer met1    Track-Pitch = 0.3700  line-2-Via Pitch: 0.3250
+[INFO GRT-0019] Found 0 clock nets.
+[INFO GRT-0001] Minimum degree: 2147483647
+[INFO GRT-0002] Maximum degree: 1
+[WARNING GRT-0038] Found blockage outside die area in instance buffer.
+[WARNING GRT-0038] Found blockage outside die area in instance buffer.
+[INFO GRT-0003] Macros: 0
+[INFO GRT-0004] Blockages: 11
+
+[INFO GRT-0053] Routing resources analysis:
+          Routing      Original      Derated      Resource
+Layer     Direction    Resources     Resources    Reduction (%)
+---------------------------------------------------------------
+li1        Vertical           12             0          100.00%
+met1       Horizontal          9             0          100.00%
+---------------------------------------------------------------
+
+
+[INFO GRT-0096] Final congestion report:
+Layer         Resource        Demand        Usage (%)    Max H / Max V / Total Overflow
+---------------------------------------------------------------------------------------
+li1                  0             0            0.00%             0 /  0 /  0
+met1                 0             0            0.00%             0 /  0 /  0
+---------------------------------------------------------------------------------------
+Total                0             0            0.00%             0 /  0 /  0
+
+[INFO GRT-0018] Total wirelength: 0 um
+[INFO GRT-0014] Routed nets: 2
+No differences found.

src/grt/test/single_row.tcl

@@ -0,0 +1,14 @@
+# check if global route works for single row designs
+source "helpers.tcl"
+read_liberty "sky130hs/sky130_fd_sc_hs__tt_025C_1v80.lib"
+read_lef "sky130hs/sky130hs.tlef"
+read_lef "sky130hs/sky130hs_std_cell.lef"
+read_def single_row.def
+
+set guide_file [make_result_file single_row.guide]
+
+global_route -verbose
+
+write_guides $guide_file
+
+diff_file single_row.guideok $guide_file