visitConnectedPins, term & net iterator, update use of term, net(pin)…

… for modbterm/moditerm
andyfox-rushc · Feb 29, 2024 · dd699c9 · dd699c9
1 parent e846ef1
commit dd699c9
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Showing 5 changed files with 5 additions and 7 deletions.
diff --git a/src/dbSta/test/hier2.tcl b/src/dbSta/test/hier2.tcl
@@ -4,7 +4,6 @@ read_lef example1.lef
 read_liberty example1_typ.lib
 read_verilog hier2.v
 link_design top
-write_db hier2.db
 write_verilog hier2_out.v
 diff_files hier2_out.v hier2_out.vok
 
diff --git a/src/dbSta/test/hier2_out.vok b/src/dbSta/test/hier2_out.vok
@@ -12,7 +12,6 @@ module top (a,
  gate1 gate2_inst (.zn(out),
     .a2(b),
     .a1(a_int));
- assign out = out;
 endmodule
 module gate1 (zn,
     a2,
@@ -25,5 +24,4 @@ module gate1 (zn,
  AND2_X1 \gate2_inst/_5_  (.ZN(zn),
     .A1(a1),
     .A2(a2));
- assign zn = out;
 endmodule
diff --git a/src/dbSta/test/sdc_get1.tcl b/src/dbSta/test/sdc_get1.tcl
@@ -3,5 +3,6 @@ source "helpers.tcl"
 read_lef example1.lef
 read_def example1.def
 read_liberty example1_slow.lib
+write_verilog noise.v
 report_object_names [get_ports -of_objects [get_nets clk1]]
 report_object_full_names [get_pins -of_objects [get_nets clk1]]
diff --git a/src/dft/test/sub_modules_sky130.v b/src/dft/test/sub_modules_sky130.v
@@ -4,14 +4,16 @@ module sub_modules(port1, clock, output1, set_b);
   input set_b;
   output output1;
 
- shift_register_2b my_shift_register(port1, output1, clock);
+ shift_register_2b my_shift_register(port1, output1, set_b,clock);
 
 endmodule
 
-module shift_register_2b(from, to, clock);
+module shift_register_2b(from, to, set_b, clock);
   input from;
   output to;
   input clock;
+  input set_b;
+
   wire net1;
 
   sky130_fd_sc_hd__dfstp_1 ff1(

diff --git a/src/dft/test/sub_modules_sky130.vok b/src/dft/test/sub_modules_sky130.vok
@@ -19,7 +19,6 @@ module sub_modules (clock,
     .set_b(set_b),
     .to(output1),
     .from(port1));
- assign output1 = output1;
  assign scan_out_1 = \my_shift_register/net1 ;
 endmodule
 module shift_register_2b (clock,
@@ -44,5 +43,4 @@ module shift_register_2b (clock,
     .SCE(scan_enable_1),
     .SET_B(set_b),
     .CLK(clock));
- assign to = output1;
 endmodule