Fix test cases failures related to little endian instructions

angr · Nov 17, 2023 · 782cef2 · 782cef2
1 parent 09e038f
commit 782cef2
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Showing 3 changed files with 11 additions and 8 deletions.
diff --git a/pyvex/__init__.py b/pyvex/__init__.py
@@ -10,6 +10,7 @@
     ARCH_ARM64_BE,
     ARCH_ARM64_LE,
     ARCH_ARM_BE,
+    ARCH_ARM_BE_LE,
     ARCH_ARM_LE,
     ARCH_MIPS32_BE,
     ARCH_MIPS32_LE,
@@ -72,8 +73,9 @@
     "IRConst",
     "ARCH_X86",
     "ARCH_AMD64",
-    "ARCH_ARM_LE",
     "ARCH_ARM_BE",
+    "ARCH_ARM_BE_LE",
+    "ARCH_ARM_LE",
     "ARCH_ARM64_LE",
     "ARCH_ARM64_BE",
     "ARCH_PPC32",

diff --git a/pyvex/arches.py b/pyvex/arches.py
@@ -10,11 +10,11 @@ class PyvexArch:
     An architecture definition for use with pyvex - usable version.
     """
 
-    def __init__(self, name: str, bits: int, memory_endness: str):
+    def __init__(self, name: str, bits: int, memory_endness: str, instruction_endness: str = "Iend_BE"):
         self.name = name
         self.bits = bits
         self.memory_endness = memory_endness
-        self.instruction_endness = "Iend_BE"
+        self.instruction_endness = instruction_endness
         self.byte_width = 8
         self.register_list: List[Register] = []
         self.registers: Dict[str, Tuple[int, int]] = {}
@@ -60,17 +60,18 @@ def translate_register_name(self, offset, size=None):  # pylint: disable=unused-
         for (arch, reg), offset2 in guest_offsets.items():
             if arch == self.vex_name_small and offset2 == offset:
                 return reg
-        return None
+        return str(offset)
 
     def get_register_offset(self, name: str) -> int:
         return guest_offsets[(self.vex_name_small, name)]
 
 
 ARCH_X86 = PyvexArch("X86", 32, "Iend_LE")
 ARCH_AMD64 = PyvexArch("AMD64", 64, "Iend_LE")
-ARCH_ARM_LE = PyvexArch("ARM", 32, "Iend_LE")
+ARCH_ARM_LE = PyvexArch("ARM", 32, "Iend_LE", instruction_endness="Iend_LE")
+ARCH_ARM_BE_LE = PyvexArch("ARM", 32, "Iend_BE", instruction_endness="Iend_LE")
 ARCH_ARM_BE = PyvexArch("ARM", 32, "Iend_LE")
-ARCH_ARM64_LE = PyvexArch("ARM64", 64, "Iend_LE")
+ARCH_ARM64_LE = PyvexArch("ARM64", 64, "Iend_LE", instruction_endness="Iend_LE")
 ARCH_ARM64_BE = PyvexArch("ARM64", 64, "Iend_BE")
 ARCH_PPC32 = PyvexArch("PPC32", 32, "Iend_BE")
 ARCH_PPC64_BE = PyvexArch("PPC64", 64, "Iend_BE")

diff --git a/tests/test_arm_postprocess.py b/tests/test_arm_postprocess.py
@@ -322,7 +322,7 @@ def test_arm_postprocess_ret():
         irsb = pyvex.IRSB(
             data=b"\xe9\x1b\xa8\xf0",
             mem_addr=0xED4028,
-            arch=pyvex.ARCH_ARM_BE,
+            arch=pyvex.ARCH_ARM_BE_LE,
             num_inst=1,
             opt_level=i,
         )
@@ -333,7 +333,7 @@ def test_arm_postprocess_ret():
         irsb = pyvex.IRSB(
             data=b"\xe9\x1b\xa8\xf0",
             mem_addr=0x4D4028,
-            arch=pyvex.ARCH_ARM_BE,
+            arch=pyvex.ARCH_ARM_BE_LE,
             num_inst=1,
             opt_level=i,
         )