WIP: BUILD.bazel: Update L1MetadataArray

Signed-off-by: Illia Vysochyn <[email protected]>
antmicro · Jul 31, 2024 · 3b3c05b · 3b3c05b
1 parent 49f32c0
commit 3b3c05b
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Showing 2 changed files with 9 additions and 6 deletions.
diff --git a/BUILD.bazel b/BUILD.bazel
@@ -203,29 +203,27 @@ orfs_flow(
     macros = ["tag_array_64x184_generate_abstract"],
     stage_args = {
         "synth": {
+            "SDC_FILE": "$(location :test/constraints-top.sdc)",
             "SYNTH_HIERARCHICAL": "1",
-            "SDC_FILE": "$(location :constraints-sram)",
         },
         "floorplan": {
             "CORE_UTILIZATION": "3",
             "RTLMP_FLOW": "True",
             "CORE_MARGIN": "2",
-            "IO_CONSTRAINTS": "$(location :io)",
+            "MACRO_PLACE_HALO": "30 30",
         },
         "place": {
             "PLACE_DENSITY": "0.20",
             "PLACE_PINS_ARGS": "-annealing",
-            "IO_CONSTRAINTS": "$(location :io)",
         },
     },
     stage_sources = {
-        "synth": [":constraints-sram"],
-        "floorplan": [":io"],
-        "place": [":io"],
+        "synth": [":test/constraints-top.sdc"],
     },
     verilog_files = ["//rtl:L1MetadataArray.sv"],
 )
 
+
 boom_tile_macros = \
     [x + "_generate_abstract" for x in boom_tile_rams] + \
     [x + "_generate_abstract" for x in boom_regfile_rams] + \

diff --git a/test/constraints-top.sdc b/test/constraints-top.sdc
@@ -0,0 +1,5 @@
+set clk_name clock
+set clk_port_name clock
+set clk_period 2000
+
+source $env(PLATFORM_DIR)/constraints.sdc