Update LiteDRAM and LiteX for better DDR5 support

Internal tag [#49418] Signed-off-by: Maciej Dudek <[email protected]>
antmicro · Sep 19, 2023 · 6092bc2 · 6092bc2
1 parent b59812e
commit 6092bc2
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Showing 3 changed files with 4 additions and 4 deletions.
diff --git a/rowhammer_tester/targets/common.py b/rowhammer_tester/targets/common.py
@@ -571,13 +571,13 @@ def run(args, builder, build_kwargs, target_name):
         print(f"Loading BIOS from: {bios_bin} starting at 0x{wb.mems.rom.base:08x} ...")
 
         print('Stopping CPU')
-        wb.regs.ctrl_reset.write(0b10)  # cpu_rst
+        wb.regs.ctrl__reset.write(0b10)  # cpu_rst
 
         memwrite(wb, rom_data, base=wb.mems.rom.base)
         wb.read(wb.mems.rom.base)
 
         print('Rebooting CPU')
-        wb.regs.ctrl_reset.write(0)
+        wb.regs.ctrl__reset.write(0)
 
         wb.close()
 

diff --git a/third_party/litedram b/third_party/litedram
diff --git a/third_party/litex b/third_party/litex