Update DDR5 S7CRG

Signed-off-by: Maciej Dudek <[email protected]>
antmicro · Mar 26, 2024 · befa5a0 · befa5a0
1 parent 705bf1b
commit befa5a0
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Showing 4 changed files with 34 additions and 10 deletions.
diff --git a/rowhammer_tester/targets/ddr5_test_board.py b/rowhammer_tester/targets/ddr5_test_board.py
@@ -135,7 +135,8 @@ def __init__(self, platform, sys_clk_freq, iodelay_clk_freq):
         # BUFMR to BUFR and BUFIO, "raw" clocks
         self.clock_domains.cd_sys4x_raw    = ClockDomain(reset_less=True)
         self.clock_domains.cd_sys4x_90_raw = ClockDomain(reset_less=True)
-        # BUFMR reset domain
+        # BUFMR reset domains
+        self.clock_domains.cd_sys2x_rst = ClockDomain()
         self.clock_domains.cd_sys2x_90_rst = ClockDomain()
 
         # # #
@@ -160,14 +161,20 @@ def __init__(self, platform, sys_clk_freq, iodelay_clk_freq):
             buf=None,
             platform=platform
         )
+        mmcm.create_clkout(
+            self.cd_sys2x_rst,
+            2 * sys_clk_freq,
+            clock_out = 0,
+            div       = 2,
+            buf       = 'bufr',
+        )
         mmcm.create_clkout(
             self.cd_sys2x_90_rst,
             2 * sys_clk_freq,
             clock_out = 1,
             div       = 2,
             phase     = 90,
             buf       = 'bufr',
-            name      = 'rst_domain',
         )
 
         mmcm.create_clkout(self.cd_sys,   sys_clk_freq)
@@ -208,7 +215,8 @@ def get_ddr_pin_domains(self):
 
     def get_ddrphy(self):
         PHYCRG = ddr5.S7PHYCRG(
-            reset_clock_domain = "sys2x_90_rst",
+            reset_clock_domain = "sys2x_rst",
+            reset_clock_90_domain = "sys2x_90_rst",
             source_4x          = ClockSignal("sys4x_raw"),
             source_4x_90       = ClockSignal("sys4x_90_raw"),
         )

diff --git a/rowhammer_tester/targets/ddr5_tester.py b/rowhammer_tester/targets/ddr5_tester.py
@@ -29,7 +29,8 @@ def __init__(self, platform, sys_clk_freq, iodelay_clk_freq):
         # BUFMR to BUFR and BUFIO, "raw" clocks
         self.clock_domains.cd_sys4x_raw    = ClockDomain(reset_less=True)
         self.clock_domains.cd_sys4x_90_raw = ClockDomain(reset_less=True)
-        # BUFMR reset domain
+        # BUFMR reset domains
+        self.clock_domains.cd_sys2x_rst = ClockDomain()
         self.clock_domains.cd_sys2x_90_rst = ClockDomain()
 
         # # #
@@ -53,14 +54,20 @@ def __init__(self, platform, sys_clk_freq, iodelay_clk_freq):
             with_reset=False,
             buf=None,
         )
+        mmcm.create_clkout(
+            self.cd_sys2x_rst,
+            2 * sys_clk_freq,
+            clock_out = 0,
+            div       = 2,
+            buf       = 'bufr',
+        )
         mmcm.create_clkout(
             self.cd_sys2x_90_rst,
             2 * sys_clk_freq,
             clock_out = 1,
             div       = 2,
             phase     = 90,
             buf       = 'bufr',
-            name      = "rst_domain",
         )
 
         mmcm.create_clkout(self.cd_sys,    sys_clk_freq)
@@ -128,7 +135,8 @@ def get_ddr_pin_domains(self):
 
     def get_ddrphy(self):
         PHYCRG = ddr5.S7PHYCRG(
-            reset_clock_domain = "sys2x_90_rst",
+            reset_clock_domain = "sys2x_rst",
+            reset_clock_90_domain = "sys2x_90_rst",
             source_4x          = ClockSignal("sys4x_raw"),
             source_4x_90       = ClockSignal("sys4x_90_raw"),
         )

diff --git a/rowhammer_tester/targets/sodimm_ddr5_tester.py b/rowhammer_tester/targets/sodimm_ddr5_tester.py
@@ -30,7 +30,8 @@ def __init__(self, platform, sys_clk_freq, iodelay_clk_freq):
         # BUFMR to BUFR and BUFIO, "raw" clocks
         self.clock_domains.cd_sys4x_raw    = ClockDomain(reset_less=True)
         self.clock_domains.cd_sys4x_90_raw = ClockDomain(reset_less=True)
-        # BUFMR reset domain
+        # BUFMR reset domains
+        self.clock_domains.cd_sys2x_rst = ClockDomain()
         self.clock_domains.cd_sys2x_90_rst = ClockDomain()
 
         # # #
@@ -54,14 +55,20 @@ def __init__(self, platform, sys_clk_freq, iodelay_clk_freq):
             with_reset=False,
             buf=None,
         )
+        mmcm.create_clkout(
+            self.cd_sys2x_rst,
+            2 * sys_clk_freq,
+            clock_out = 0,
+            div       = 2,
+            buf       = 'bufr',
+        )
         mmcm.create_clkout(
             self.cd_sys2x_90_rst,
             2 * sys_clk_freq,
             clock_out = 1,
             div       = 2,
             phase     = 90,
             buf       = 'bufr',
-            name      = "rst_domain",
         )
 
         mmcm.create_clkout(self.cd_sys,    sys_clk_freq)
@@ -217,7 +224,8 @@ def get_ddr_pin_domains(self):
 
     def get_ddrphy(self):
         PHYCRG = ddr5.S7PHYCRG(
-            reset_clock_domain = "sys2x_90_rst",
+            reset_clock_domain = "sys2x_rst",
+            reset_clock_90_domain = "sys2x_90_rst",
             source_4x          = ClockSignal("sys4x_raw"),
             source_4x_90       = ClockSignal("sys4x_90_raw"),
         )

diff --git a/third_party/litedram b/third_party/litedram