[#65952] Add wireframe images of boards

antmicro · Oct 8, 2024 · c7360f7 · c7360f7
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diff --git a/docs/source/data_center_rdimm_ddr4_tester.md b/docs/source/data_center_rdimm_ddr4_tester.md
@@ -0,0 +1,82 @@
+# Data Center RDIMM DDR4 Tester
+
+```{image} images/data-center-rdimm-ddr4-tester-1.2.0.png
+```
+
+The Data Center RDIMM DDR4 Tester is an open source hardware test platform that enables testing and experimenting with various DDR4 RDIMMs (Registered Dual In-Line Memory Module).
+
+The hardware is open and can be found on GitHub:
+<https://github.com/antmicro/data-center-dram-tester/>
+
+The following instructions explain how to set up the board.
+
+## IO map
+A map of on-board connectors, status LEDs, control buttons and I/O interfaces is provided below.
+
+:::{figure-md}
+![](images/data-center-rdimm-ddr4-tester-descriptions.png)
+
+DDR4 data center dram tester interface map
+:::
+
+Connectors:
+* [`J3`](#data-center-dram-tester_J3) - main DC barrel jack power connector, voltage between 7-15V is supported
+* [`J9`](#data-center-dram-tester_J9) - USB-C debug connector used for programming FPGA or Flash memory
+* [`J1`](#data-center-dram-tester_J1) - standard 14-pin JTAG connector used for programming FPGA or Flash memory
+* [`J6`](#data-center-dram-tester_J6) - HDMI connector
+* [`J2`](#data-center-dram-tester_J2) - Ethernet connector used for data exchange with on-board FPGA and power supply via PoE
+* [`U14`](#data-center-dram-tester_U14) - 288-pin RDIMM connector for connecting DDR4 memory modules
+* [`J8`](#data-center-dram-tester_J8) - optional 5V fan connector
+* [`J7`](#data-center-dram-tester_J7) - socket for SD card
+* [`J5`](#data-center-dram-tester_J5) - FMC HPC connector reserved for future use
+
+Switches and buttons:
+* Power ON/OFF button [`S3`](#data-center-dram-tester_S3) - push button to power up a device, hold for 8s to turn the device off
+* FPGA programming button [`PROG_B1`](#data-center-dram-tester_PROG_B1) - push button to start programming from Flash
+* Configuration mode selector [`S2`](#data-center-dram-tester_S2) - Swipe left/right to specify SPI/JTAG programming mode
+* HOT SWAP eject button [`S1`](#data-center-dram-tester_S1) - reserved for future use to turn off a DDR memory and allow hot swapping it
+
+LEDs:
+* 3V3 Power indicator [`PWR1`](#data-center-dram-tester_PWR1) - indicates presence of stabilized 3.3V voltage
+* PoE indicator [`D15`](#data-center-dram-tester_D15) - indicates negotiated PoE voltage supply
+* FPGA programming INIT [`D10`](#data-center-dram-tester_D10) - indicates current FPGA configuration state
+* FPGA programming DONE [`D1`](#data-center-dram-tester_D1) - indicates completion of FPGA programming
+* HOT SWAP status [`D17`](#data-center-dram-tester_D17) - RGY LED indicating status of hot swap process
+* 5x User ([`D5`](#data-center-dram-tester_D5), [`D6`](#data-center-dram-tester_D6), [`D7`](#data-center-dram-tester_D7), [`D8`](#data-center-dram-tester_D8), [`D9`](#data-center-dram-tester_D9)) - LEDs for user's definition
+
+## Board configuration
+
+Connect power supply (7-15VDC) to [`J3`](#data-center-dram-tester_J3) barrel jack. Then connect the board USB cable ([`J9`](#data-center-dram-tester_J9)) and Ethernet cable ([`J2`](#data-center-dram-tester_J2)) to your computer and insert the memory module to the socket [`U14`](#data-center-dram-tester_U14).
+To turn the board on, use power switch [`S3`](#data-center-dram-tester_S3). 
+
+After power is up, configure the network. The board's IP address will be `192.168.100.50` (so you could e.g. use `192.168.100.2/24`). The `IP_ADDRESS` environment variable can be used to modify the board's address.
+
+Next, generate the FPGA bitstream:
+
+```sh
+export TARGET=ddr4_datacenter_test_board
+make build
+```
+
+```{note}
+By typing `make` (without `build`) LiteX will generate build files without invoking Vivado.
+```
+
+The results will be located in: `build/ddr4_datacenter_test_board/gateware/antmicro_datacenter_ddr4_test_board.bit`. To upload it, use:
+
+```sh
+export TARGET=ddr4_datacenter_test_board
+make upload
+```
+
+To save bitstream in flash memory, use:
+
+```sh
+export TARGET=ddr4_datacenter_test_board
+make flash
+```
+
+There is a JTAG/SPI switch [`S2`](#data-center-rdimm-ddr4-tester_S2) on the right side of the board, near JTAG connector.
+It defines whether the bitstream will be loaded via JTAG or SPI Flash memory.
+
+Bitstream will be loaded from flash memory upon device power-on or after a [`PROG_B1`](#data-center-dram-tester_PROG_B1) button press.
diff --git a/docs/source/ddr5_tester.md → docs/source/data_center_rdimm_ddr5_tester.md b/docs/source/ddr5_tester.md → docs/source/data_center_rdimm_ddr5_tester.md
@@ -10,6 +10,38 @@ The hardware is open and can be found on GitHub:
 
 The following instructions explain how to set up the board.
 
+## IO map
+A map of on-board connectors, status LEDs, control buttons and I/O interfaces is provided below.
+
+:::{figure-md}
+![](images/rdimm-ddr5-tester-descriptions.png)
+
+DDR5 tester interface map
+:::
+
+Connectors:
+* [`J1`](#ddr5-tester_J1) - main DC barrel jack power connector, voltage between 12-15V is supported
+* [`J6`](#ddr5-tester_J6) - USB Micro-B debug connector used for programming FPGA or Flash memory
+* [`J3`](#ddr5-tester_J3) - standard 14-pin JTAG connector used for programming FPGA or Flash memory
+* [`J5`](#ddr5-tester_J5) - HDMI connector
+* [`J4`](#ddr5-tester_J4) - Ethernet connector used for data exchange with on-board FPGA
+* [`U12`](#ddr5-tester_U12) - 288-pin RDIMM connector for connecting DDR5 memory modules
+* [`MODE1`](#ddr5-tester_MODE1) - configuration mode selector, short proper pins with jumper to specify programming mode
+* [`J2`](#ddr5-tester_J2) - optional 5V fan connector
+* [`J7`](#ddr5-tester_J7) - socket for SD card
+* [`J8`](#ddr5-tester_J8) - 2.54mm goldpin connector with exposed I2C and I3C signals
+
+Switches and buttons:
+* Power ON/OFF button [`S1`](#ddr5-tester_S1) - swipe up to power up a device, swipe down to turn the device off
+* FPGA programming button [`PROG_B1`](#ddr5-tester_PROG_B1) - push button to start programming from Flash
+* 4x User button ([`PROG_B2`](#ddr5-tester_PROG_B2), [`PROG_B3`](#ddr5-tester_PROG_B3), [`PROG_B4`](#ddr5-tester_PROG_B4), [`PROG_B5`](#ddr5-tester_PROG_B5)) - buttons for user's definition
+
+LEDs:
+* 3V3 Power indicator [`PWR1`](#ddr5-tester_PWR1) - indicates presence of stabilized 3.3V voltage
+* FPGA programming INIT [`D6`](#ddr5-tester_D6) - indicates current FPGA configuration state
+* FPGA programming DONE [`D5`](#ddr5-tester_D5) - indicates completion of FPGA programming
+* 5x User ([`D7`](#ddr5-tester_D7), [`D8`](#ddr5-tester_D8), [`D9`](#ddr5-tester_D9), [`D10`](#ddr5-tester_D10), [`D11`](#ddr5-tester_D11)) - LEDs for user's definition
+
 ## Rowhammer Tester Target Configuration
 
 Connect power supply (12-15VDC) to [`J1`](#ddr5-tester_J1) barrel jack. Then connect the board USB cable ([`J6`](#ddr5-tester_J6)) and Ethernet cable ([`J4`](#ddr5-tester_J4)) to your computer and insert the memory module to the socket [`U12`](#ddr5-tester_U12).

diff --git a/docs/source/ddr4_datacenter_dram_tester.md b/docs/source/ddr4_datacenter_dram_tester.md
diff --git a/docs/source/images/data-center-dram-tester/D1.png b/docs/source/images/data-center-dram-tester/D1.png
diff --git a/docs/source/images/data-center-dram-tester/D10.png b/docs/source/images/data-center-dram-tester/D10.png
diff --git a/docs/source/images/data-center-dram-tester/D15.png b/docs/source/images/data-center-dram-tester/D15.png
diff --git a/docs/source/images/data-center-dram-tester/D17.png b/docs/source/images/data-center-dram-tester/D17.png
diff --git a/docs/source/images/data-center-dram-tester/D5.png b/docs/source/images/data-center-dram-tester/D5.png
diff --git a/docs/source/images/data-center-dram-tester/D6.png b/docs/source/images/data-center-dram-tester/D6.png
diff --git a/docs/source/images/data-center-dram-tester/D7.png b/docs/source/images/data-center-dram-tester/D7.png
diff --git a/docs/source/images/data-center-dram-tester/D8.png b/docs/source/images/data-center-dram-tester/D8.png
diff --git a/docs/source/images/data-center-dram-tester/D9.png b/docs/source/images/data-center-dram-tester/D9.png
diff --git a/docs/source/images/data-center-dram-tester/J2.png b/docs/source/images/data-center-dram-tester/J2.png
diff --git a/docs/source/images/data-center-dram-tester/J3.png b/docs/source/images/data-center-dram-tester/J3.png
diff --git a/docs/source/images/data-center-dram-tester/J6.png b/docs/source/images/data-center-dram-tester/J6.png
diff --git a/docs/source/images/data-center-dram-tester/J8.png b/docs/source/images/data-center-dram-tester/J8.png
diff --git a/docs/source/images/data-center-dram-tester/J9.png b/docs/source/images/data-center-dram-tester/J9.png
diff --git a/docs/source/images/data-center-dram-tester/M1.png b/docs/source/images/data-center-dram-tester/M1.png
diff --git a/docs/source/images/data-center-dram-tester/PROG_B1.png b/docs/source/images/data-center-dram-tester/PROG_B1.png
diff --git a/docs/source/images/data-center-dram-tester/PWR1.png b/docs/source/images/data-center-dram-tester/PWR1.png
diff --git a/docs/source/images/data-center-dram-tester/S1.png b/docs/source/images/data-center-dram-tester/S1.png
diff --git a/docs/source/images/data-center-dram-tester/S2.png b/docs/source/images/data-center-dram-tester/S2.png
diff --git a/docs/source/images/data-center-dram-tester/S3.png b/docs/source/images/data-center-dram-tester/S3.png
diff --git a/docs/source/images/data-center-dram-tester/U14.png b/docs/source/images/data-center-dram-tester/U14.png
diff --git a/docs/source/images/data-center-dram-tester/U15.png b/docs/source/images/data-center-dram-tester/U15.png
diff --git a/docs/source/images/data-center-rdimm-ddr4-tester-descriptions.png b/docs/source/images/data-center-rdimm-ddr4-tester-descriptions.png
diff --git a/docs/source/images/lpddr4-test-board-descriptions.png b/docs/source/images/lpddr4-test-board-descriptions.png
diff --git a/docs/source/images/rdimm-ddr5-tester-descriptions.png b/docs/source/images/rdimm-ddr5-tester-descriptions.png
diff --git a/docs/source/images/sodimm-ddr5-tester-descriptions.png b/docs/source/images/sodimm-ddr5-tester-descriptions.png
diff --git a/docs/source/images/sodimm-ddr5-tester/D1.png b/docs/source/images/sodimm-ddr5-tester/D1.png
diff --git a/docs/source/images/sodimm-ddr5-tester/D10.png b/docs/source/images/sodimm-ddr5-tester/D10.png
diff --git a/docs/source/images/sodimm-ddr5-tester/D11.png b/docs/source/images/sodimm-ddr5-tester/D11.png
diff --git a/docs/source/images/sodimm-ddr5-tester/D12.png b/docs/source/images/sodimm-ddr5-tester/D12.png
diff --git a/docs/source/images/sodimm-ddr5-tester/D13.png b/docs/source/images/sodimm-ddr5-tester/D13.png
diff --git a/docs/source/images/sodimm-ddr5-tester/D2.png b/docs/source/images/sodimm-ddr5-tester/D2.png
diff --git a/docs/source/images/sodimm-ddr5-tester/D3.png b/docs/source/images/sodimm-ddr5-tester/D3.png
diff --git a/docs/source/images/sodimm-ddr5-tester/D4.png b/docs/source/images/sodimm-ddr5-tester/D4.png
diff --git a/docs/source/images/sodimm-ddr5-tester/D5.png b/docs/source/images/sodimm-ddr5-tester/D5.png
diff --git a/docs/source/images/sodimm-ddr5-tester/D6.png b/docs/source/images/sodimm-ddr5-tester/D6.png
diff --git a/docs/source/images/sodimm-ddr5-tester/D7.png b/docs/source/images/sodimm-ddr5-tester/D7.png
diff --git a/docs/source/images/sodimm-ddr5-tester/D8.png b/docs/source/images/sodimm-ddr5-tester/D8.png
diff --git a/docs/source/images/sodimm-ddr5-tester/D9.png b/docs/source/images/sodimm-ddr5-tester/D9.png
diff --git a/docs/source/images/sodimm-ddr5-tester/H2.png b/docs/source/images/sodimm-ddr5-tester/H2.png
diff --git a/docs/source/images/sodimm-ddr5-tester/J2.png b/docs/source/images/sodimm-ddr5-tester/J2.png
diff --git a/docs/source/images/sodimm-ddr5-tester/J3.png b/docs/source/images/sodimm-ddr5-tester/J3.png
diff --git a/docs/source/images/sodimm-ddr5-tester/J4.png b/docs/source/images/sodimm-ddr5-tester/J4.png
diff --git a/docs/source/images/sodimm-ddr5-tester/J5.png b/docs/source/images/sodimm-ddr5-tester/J5.png
diff --git a/docs/source/images/sodimm-ddr5-tester/J6.png b/docs/source/images/sodimm-ddr5-tester/J6.png
diff --git a/docs/source/images/sodimm-ddr5-tester/J7.png b/docs/source/images/sodimm-ddr5-tester/J7.png
diff --git a/docs/source/images/sodimm-ddr5-tester/J8.png b/docs/source/images/sodimm-ddr5-tester/J8.png
diff --git a/docs/source/images/sodimm-ddr5-tester/SW1.png b/docs/source/images/sodimm-ddr5-tester/SW1.png
diff --git a/docs/source/images/sodimm-ddr5-tester/SW2.png b/docs/source/images/sodimm-ddr5-tester/SW2.png
diff --git a/docs/source/images/sodimm-ddr5-tester/SW3.png b/docs/source/images/sodimm-ddr5-tester/SW3.png
diff --git a/docs/source/images/sodimm-ddr5-tester/SW4.png b/docs/source/images/sodimm-ddr5-tester/SW4.png
diff --git a/docs/source/images/sodimm-ddr5-tester/SW5.png b/docs/source/images/sodimm-ddr5-tester/SW5.png
diff --git a/docs/source/images/sodimm-ddr5-tester/SW6.png b/docs/source/images/sodimm-ddr5-tester/SW6.png
diff --git a/docs/source/images/sodimm-ddr5-tester/U4.png b/docs/source/images/sodimm-ddr5-tester/U4.png
diff --git a/docs/source/index.md b/docs/source/index.md
@@ -15,11 +15,11 @@ dram_modules.md
 
 arty.md
 zcu104.md
-lpddr4_tb.md
-ddr5_test_board.md
-ddr4_datacenter_dram_tester.md
-ddr5_tester.md
-sodimm_ddr5_tester.md
+lpddr4_test_board.md
+lpddr4_test_board_with_ddr5_testbed.md
+data_center_rdimm_ddr4_tester.md
+data_center_rdimm_ddr5_tester.md
+so_dimm_ddr5_tester.md
 ```
 
 ```{toctree}

diff --git a/docs/source/lpddr4_tb.md b/docs/source/lpddr4_tb.md
diff --git a/docs/source/lpddr4_test_board.md b/docs/source/lpddr4_test_board.md
@@ -0,0 +1,85 @@
+# LPDDR4 Test Board
+
+```{image} images/lpddr4-test-board.jpg
+```
+
+LPDDR4 Test Board is a platform developed by Antmicro for testing LPDDR4 memory.
+It uses Xilinx Kintex-7 FPGA (XC7K70T-FBG484) and by default includes a custom SO-DIMM module with Micron's MT53E256M16D1 LPDDR4 DRAM.
+
+The hardware is open and can be found on GitHub:
+
+- Test board: <https://github.com/antmicro/lpddr4-test-board>
+- Testbed: <https://github.com/antmicro/lpddr4-testbed>
+
+## IO map
+A map of on-board connectors, status LEDs, control buttons and I/O interfaces is provided below.
+
+:::{figure-md}
+![](images/lpddr4-test-board-descriptions.png)
+
+LPDDR4 test board interface map
+:::
+
+Connectors:
+* [`J6`](#lpddr4-test-board_J6) - main DC barrel jack power connector, voltage between 7-15V is supported
+* [`J1`](#lpddr4-test-board_J1) - USB Micro-B debug connector used for programming FPGA or Flash memory
+* [`J4`](#lpddr4-test-board_J4) - standard 14-pin JTAG connector used for programming FPGA or Flash memory
+* [`J2`](#lpddr4-test-board_J2) - HDMI connector
+* [`J5`](#lpddr4-test-board_J5) - Ethernet connector used for data exchange with on-board FPGA
+* [`J9`](#lpddr4-test-board_J9) - 260-pin SO-DIMM connector for connecting LPDDR4 memory
+* [`MODE1`](#lpddr4-test-board_MODE1) - configuration mode selector, short proper pins with jumper to specify programming mode
+* [`J7`](#lpddr4-test-board_J7) - VDDQ selector used for specifying value of VDDQ voltage
+* [`J8`](#lpddr4-test-board_J8) - optional 5V fan connector
+* [`J3`](#lpddr4-test-board_J3) - socket for SD card
+
+Switches and buttons:
+* Power switch [`S1`](#lpddr4-test-board_S1) - swipe up to power up a device, swipe down to turn the device off
+* FPGA programming button [`PROG_B1`](#lpddr4-test-board_PROG_B1) - push to start programming from Flash
+* 4x User button ([`USR_BTN1`](#lpddr4-test-board_USR_BTN1),[`USR_BTN2`](#lpddr4-test-board_USR_BTN2),[`USR_BTN3`](#lpddr4-test-board_USR_BTN3),[`USR_BTN4`](#lpddr4-test-board_USR_BTN4)) - buttons for user's definition
+
+LEDs:
+* Power indicators ([`PWR1`](#lpddr4-test-board_PWR1), [`PWR2`](#lpddr4-test-board_PWR2), [`PWR3`](#lpddr4-test-board_PWR3), [`PWR4`](#lpddr4-test-board_PWR4), [`PWR5`](#lpddr4-test-board_PWR5), [`PWR6`](#lpddr4-test-board_PWR6)) - indicates presence of stabilized voltages: 5V, 3V3, 1V8, 1V2, 1V1, 1V0
+* FPGA programming INIT [`D9`](#lpddr4-test-board_D9) - indicates current FPGA configuration state
+* FPGA programming DONE [`D8`](#lpddr4-test-board_D8) - indicates completion of FPGA programming
+* 5x User ([`D1`](#lpddr4-test-board_D1), [`D2`](#lpddr4-test-board_D2), [`D3`](#lpddr4-test-board_D3), [`D5`](#lpddr4-test-board_D5), [`D6`](#lpddr4-test-board_D6)) - LEDs for user's definition
+
+## Board configuration
+
+First insert the LPDDR4 DRAM module into the socket [`J9`](#lpddr4-test-board_J9) and make sure that jumpers are set in correct positions:
+
+- VDDQ switch ([`J7`](#lpddr4-test-board_J7)) should be set in position 1V1
+- [`MODE1`](#lpddr4-test-board_MODE1) switch should be set in position FLASH
+
+Connect power supply (7-15VDC) to [`J6`](#lpddr4-test-board_J6) barrel jack.
+Then connect the board's USB-C [`J1`](#lpddr4-test-board_J1) and Ethernet [`J5`](#lpddr4-test-board_J5) interfaces to your computer.
+Turn the board on using power switch [`S1`](#lpddr4-test-board_S1).
+Then configure the network. The board's IP address will be `192.168.100.50` (so you could e.g. use `192.168.100.2/24`). The `IP_ADDRESS` environment variable can be used to modify the board's address.
+Next, generate the FPGA bitstream:
+
+```sh
+export TARGET=lpddr4_test_board
+make build
+```
+
+The results will be located in: `build/lpddr4_test_board/gateware/antmicro_lpddr4_test_board.bit`. To upload it, use:
+
+```sh
+export TARGET=lpddr4_test_board
+make upload
+```
+
+```{note}
+By typing `make` (without `build`) LiteX will generate build files without invoking Vivado.
+```
+
+To save bitstream in flash memory, use:
+
+```sh
+export TARGET=lpddr4_test_board
+make flash
+```
+
+There is a JTAG/FLASH jumper [`MODE1`](#lpddr4-test-board_MODE1) on the right side of the board.
+It defines whether the bitstream will be loaded via JTAG or FLASH memory.
+
+Bitstream will be loaded from flash memory upon device power-on or after a FPGA programming button ([`PROG_B1`](#lpddr4-test-board_PROG_B1)) press.
diff --git a/docs/source/ddr5_test_board.md → ...ce/lpddr4_test_board_with_ddr5_testbed.md b/docs/source/ddr5_test_board.md → ...ce/lpddr4_test_board_with_ddr5_testbed.md
diff --git a/docs/source/references.md b/docs/source/references.md
@@ -1,5 +1,14 @@
 # Image references
 
+```{image} images/data-center-dram-tester/PWR1.png
+:name: data-center-dram-tester_PWR1
+```
+```{image} images/data-center-dram-tester/D1.png
+:name: data-center-dram-tester_D1
+```
+```{image} images/data-center-dram-tester/D10.png
+:name: data-center-dram-tester_D10
+```
 ```{image} images/data-center-dram-tester/D15.png
 :name: data-center-dram-tester_D15
 ```
@@ -51,7 +60,7 @@
 ```{image} images/data-center-dram-tester/S1.png
 :name: data-center-dram-tester_S1
 ```
-```{image} images/data-center-dram-tester/S3.png
+```{image} images/data-center-dram-tester/S2.png
 :name: data-center-dram-tester_S2
 ```
 ```{image} images/data-center-dram-tester/S3.png