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Refactor code to snake_case
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Signed-off-by: Michal Czyz <[email protected]>
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@mczyz-antmicro
mczyz-antmicro committed Mar 8, 2024
1 parent 77f9818 commit 965239c
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Showing 4 changed files with 64 additions and 99 deletions.
13 changes: 0 additions & 13 deletions xls/modules/dma/BUILD
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Original file line number Diff line number Diff line change
Expand Up @@ -280,19 +280,6 @@ xls_dslx_test(
library = "address_generator_lib",
)

# Address Generator Snippet
xls_dslx_library(
name = "address_generator_snippet_lib",
srcs = [
"address_generator_snippet.x",
],
)

xls_dslx_test(
name = "test_snippet",
library = "address_generator_snippet_lib",
)

xls_dslx_verilog(
name = "verilog_address_generator",
codegen_args = {
Expand Down
36 changes: 18 additions & 18 deletions xls/modules/dma/address_generator.x
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Original file line number Diff line number Diff line change
Expand Up @@ -75,7 +75,7 @@ proc AddressGenerator<ADDR_W: u32, DATA_W_DIV8: u32> {
};

let send_transfer = state.status == AddressGeneratorStatusEnum::BUSY &&
(state.it != (state.configuration.lineCount as u32));
(state.it != (state.configuration.line_count as u32));
let tok = send_if(tok, addr_gen_req, send_transfer, state.transfer);

let it = if send_transfer { state.it + u32:1 } else { state.it };
Expand All @@ -87,7 +87,7 @@ proc AddressGenerator<ADDR_W: u32, DATA_W_DIV8: u32> {
if valid_addr_gen_rsp { state.rsp_counter + u32:1 } else { state.rsp_counter };

let goto_done = (state.status == AddressGeneratorStatusEnum::BUSY) &&
(rsp_counter == (state.configuration.lineCount as u32));
(rsp_counter == (state.configuration.line_count as u32));

let tok = send_if(tok, done_ch, goto_done, u1:1);

Expand Down Expand Up @@ -128,12 +128,12 @@ proc AddressGenerator<ADDR_W: u32, DATA_W_DIV8: u32> {
address:
state.transfer.address +
(DATA_W_DIV8 as uN[ADDR_W]) *
(state.configuration.lineLength + state.configuration.lineStride),
length: state.configuration.lineLength
(state.configuration.line_length + state.configuration.line_stride),
length: state.configuration.line_length
}
} else if state.status == AddressGeneratorStatusEnum::WAIT {
TransferDescBundle<ADDR_W> {
address: configuration.startAddress, length: configuration.lineLength
address: configuration.start_address, length: configuration.line_length
}
} else {
state.transfer
Expand Down Expand Up @@ -161,15 +161,15 @@ pub fn AddressGeneratorReferenceFunction<C: u32, ADDR_W: u32, DATA_W_DIV8: u32>
update(
a, i,
TransferDescBundle<ADDR_W> {
address: config.startAddress, length: config.lineLength
address: config.start_address, length: config.line_length
})
} else {
update(
a, i,
TransferDescBundle<ADDR_W> {
address:
(a[i - u32:1]).address + DATA_W_DIV8 * (config.lineLength + config.lineStride),
length: config.lineLength
(a[i - u32:1]).address + DATA_W_DIV8 * (config.line_length + config.line_stride),
length: config.line_length
})
}
}(TransferDescBundle<ADDR_W>[C]:[common::zeroTransferDescBundle<ADDR_W>(), ...]);
Expand All @@ -181,13 +181,13 @@ fn TestAddressGeneratorReferenceFunction() {
let ADDR_W = u32:32;
let dataWidthDiv8 = u32:4;
let testConfig = MainCtrlBundle<ADDR_W> {
startAddress: uN[ADDR_W]:1000,
lineCount: uN[ADDR_W]:4,
lineLength: uN[ADDR_W]:3,
lineStride: uN[ADDR_W]:2
start_address: uN[ADDR_W]:1000,
line_count: uN[ADDR_W]:4,
line_length: uN[ADDR_W]:3,
line_stride: uN[ADDR_W]:2
};
// TODO: Is using parametric from a struct field a good practice?
let C = testConfig.lineCount;
let C = testConfig.line_count;
let a = AddressGeneratorReferenceFunction<C, ADDR_W, dataWidthDiv8>(testConfig);
assert_eq((a[0]).address, u32:1000);
assert_eq((a[1]).address, u32:1020);
Expand Down Expand Up @@ -232,10 +232,10 @@ proc TestAddressGenerator {

next(tok: token, state: u32) {
let testConfig = MainCtrlBundle<TEST_ADDR_W> {
startAddress: uN[TEST_ADDR_W]:1000,
lineCount: uN[TEST_ADDR_W]:5,
lineLength: uN[TEST_ADDR_W]:3,
lineStride: uN[TEST_ADDR_W]:0
start_address: uN[TEST_ADDR_W]:1000,
line_count: uN[TEST_ADDR_W]:5,
line_length: uN[TEST_ADDR_W]:3,
line_stride: uN[TEST_ADDR_W]:0
};

let tok = send(tok, start_ch, u1:1);
Expand All @@ -255,7 +255,7 @@ proc TestAddressGenerator {
let (tok, done, done_valid) = recv_non_blocking(tok, done_ch, u1:1);

let do_terminate = done && done_valid;
if do_terminate { assert_eq(state, testConfig.lineCount); } else { };
if do_terminate { assert_eq(state, testConfig.line_count); } else { };
let tok = send_if(tok, terminator, do_terminate, do_terminate);

state
Expand Down
23 changes: 0 additions & 23 deletions xls/modules/dma/example.x
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This file was deleted.

91 changes: 46 additions & 45 deletions xls/modules/dma/main_controller.x
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Original file line number Diff line number Diff line change
Expand Up @@ -210,17 +210,17 @@ type AdrDatPair = (uN[TEST_ADDR_W], uN[TEST_DATA_W]);

// let id = uN[TEST_ID_W]:0;
// let rw_config = MainCtrlBundle<TEST_ADDR_W> {
// startAddress: u32:0x1000, lineCount: u32:5, lineLength: u32:6, lineStride: u32:0
// start_address: u32:0x1000, line_count: u32:5, line_length: u32:6, line_stride: u32:0
// };
// let init_csr_values = AdrDatPair[u32:10]:[
// (config::READER_START_ADDRESS, rw_config.startAddress),
// (config::READER_LINE_LENGTH, rw_config.lineLength),
// (config::READER_LINE_COUNT, rw_config.lineCount),
// (config::READER_STRIDE_BETWEEN_LINES, rw_config.lineStride),
// (config::WRITER_START_ADDRESS, rw_config.startAddress),
// (config::WRITER_LINE_LENGTH, rw_config.lineLength),
// (config::WRITER_LINE_COUNT, rw_config.lineCount),
// (config::WRITER_STRIDE_BETWEEN_LINES, rw_config.lineStride),
// (config::READER_START_ADDRESS, rw_config.start_address),
// (config::READER_LINE_LENGTH, rw_config.line_length),
// (config::READER_LINE_COUNT, rw_config.line_count),
// (config::READER_STRIDE_BETWEEN_LINES, rw_config.line_stride),
// (config::WRITER_START_ADDRESS, rw_config.start_address),
// (config::WRITER_LINE_LENGTH, rw_config.line_length),
// (config::WRITER_LINE_COUNT, rw_config.line_count),
// (config::WRITER_STRIDE_BETWEEN_LINES, rw_config.line_stride),
// (config::INTERRUPT_MASK_REGISTER, uN[TEST_DATA_W]:3),
// (config::CONTROL_REGISTER, CTRL_WORD),
// ];
Expand Down Expand Up @@ -260,7 +260,7 @@ type AdrDatPair = (uN[TEST_ADDR_W], uN[TEST_DATA_W]);
// } else {};

// // Initialize system memory
// let MEM_SIZE = rw_config.lineCount * rw_config.lineLength;
// let MEM_SIZE = rw_config.line_count * rw_config.line_length;
// let system_memory = for (i, system_memory): (u32, uN[TEST_DATA_W][MEM_SIZE]) in
// u32:0..MEM_SIZE {
// update(system_memory, i, (i + u32:1) as uN[TEST_DATA_W])
Expand All @@ -269,11 +269,11 @@ type AdrDatPair = (uN[TEST_ADDR_W], uN[TEST_DATA_W]);
// // assert_eq(u32:1, u32:0);

// let system_memory_copy = for (_, mem): (u32, uN[TEST_DATA_W][MEM_SIZE]) in
// u32:0..rw_config.lineLength {
// u32:0..rw_config.line_length {
// // Handle AXI Read
// let (tok, axi_ar) = recv(tok, ch_axi_data_ar);
// let addr = (axi_ar.araddr - rw_config.startAddress) >> 2;
// let tok = for (i, tok): (u32, token) in u32:0..rw_config.lineCount {
// let addr = (axi_ar.araddr - rw_config.start_address) >> 2;
// let tok = for (i, tok): (u32, token) in u32:0..rw_config.line_count {
// let tok = send(
// tok, ch_axi_data_r,
// axi_pkg::simpleAxiRBundle<TEST_DATA_W, TEST_ID_W>(
Expand All @@ -285,10 +285,10 @@ type AdrDatPair = (uN[TEST_ADDR_W], uN[TEST_DATA_W]);

// let (tok, aw) = recv(tok, ch_axi_data_aw);

// let mem = for (i, mem): (u32, uN[TEST_DATA_W][MEM_SIZE]) in u32:0..rw_config.lineCount
// let mem = for (i, mem): (u32, uN[TEST_DATA_W][MEM_SIZE]) in u32:0..rw_config.line_count
// {
// let (tok, w) = recv(tok, ch_axi_data_w);
// let addr = (aw.awaddr - rw_config.startAddress) >> 2;
// let addr = (aw.awaddr - rw_config.start_address) >> 2;
// let mem = update(mem, addr + i, w.wdata);
// mem
// }(mem);
Expand Down Expand Up @@ -398,17 +398,17 @@ proc TestImageInverse {

let id = uN[TEST_ID_W]:0;
let rw_config = MainCtrlBundle<TEST_ADDR_W> {
startAddress: u32:0x1000, lineCount: u32:27, lineLength: u32:1, lineStride: u32:0
start_address: u32:0x1000, line_count: u32:27, line_length: u32:1, line_stride: u32:0
};
let init_csr_values = AdrDatPair[u32:10]:[
(config::READER_START_ADDRESS, rw_config.startAddress),
(config::READER_LINE_LENGTH, rw_config.lineLength),
(config::READER_LINE_COUNT, rw_config.lineCount),
(config::READER_STRIDE_BETWEEN_LINES, rw_config.lineStride),
(config::WRITER_START_ADDRESS, rw_config.startAddress),
(config::WRITER_LINE_LENGTH, rw_config.lineLength),
(config::WRITER_LINE_COUNT, rw_config.lineCount),
(config::WRITER_STRIDE_BETWEEN_LINES, rw_config.lineStride),
(config::READER_START_ADDRESS, rw_config.start_address),
(config::READER_LINE_LENGTH, rw_config.line_length),
(config::READER_LINE_COUNT, rw_config.line_count),
(config::READER_STRIDE_BETWEEN_LINES, rw_config.line_stride),
(config::WRITER_START_ADDRESS, rw_config.start_address),
(config::WRITER_LINE_LENGTH, rw_config.line_length),
(config::WRITER_LINE_COUNT, rw_config.line_count),
(config::WRITER_STRIDE_BETWEEN_LINES, rw_config.line_stride),
(config::INTERRUPT_MASK_REGISTER, uN[TEST_DATA_W]:3),
(config::CONTROL_REGISTER, CTRL_WORD),
];
Expand Down Expand Up @@ -442,7 +442,7 @@ proc TestImageInverse {
trace_fmt!("AXI Control Bus: PASS");

// Initialize system memory
let MEM_SIZE = rw_config.lineCount * rw_config.lineLength;
let MEM_SIZE = rw_config.line_count * rw_config.line_length;
let system_memory = uN[TEST_DATA_W][MEM_SIZE]:[
uN[TEST_DATA_W]:0x00, uN[TEST_DATA_W]:0x00, uN[TEST_DATA_W]:0x00, uN[TEST_DATA_W]:0x82,
uN[TEST_DATA_W]:0x04, uN[TEST_DATA_W]:0x7e, uN[TEST_DATA_W]:0x44, uN[TEST_DATA_W]:0x04,
Expand All @@ -454,11 +454,11 @@ proc TestImageInverse {
];

let system_memory_copy = for (_, mem): (u32, uN[TEST_DATA_W][MEM_SIZE]) in
u32:0..rw_config.lineLength {
u32:0..rw_config.line_length {
// Handle AXI Read
let (tok, axi_ar) = recv(tok, ch_axi_data_ar);
let addr = (axi_ar.araddr - rw_config.startAddress) >> 2;
let tok = for (i, tok): (u32, token) in u32:0..rw_config.lineCount {
let addr = (axi_ar.araddr - rw_config.start_address) >> 2;
let tok = for (i, tok): (u32, token) in u32:0..rw_config.line_count {
let tok = send(
tok, ch_axi_data_r,
axi_pkg::simpleAxiRBundle<TEST_DATA_W, TEST_ID_W>(
Expand All @@ -468,9 +468,9 @@ proc TestImageInverse {

// Handle AXI Write
let (tok, aw) = recv(tok, ch_axi_data_aw);
let mem = for (i, mem): (u32, uN[TEST_DATA_W][MEM_SIZE]) in u32:0..rw_config.lineCount {
let mem = for (i, mem): (u32, uN[TEST_DATA_W][MEM_SIZE]) in u32:0..rw_config.line_count {
let (tok, w) = recv(tok, ch_axi_data_w);
let addr = (aw.awaddr - rw_config.startAddress) >> 2;
let addr = (aw.awaddr - rw_config.start_address) >> 2;
let mem = update(mem, addr + i, w.wdata);
mem
}(mem);
Expand Down Expand Up @@ -562,17 +562,17 @@ proc TestImageInverse {
// next(tok: token, state: ()) {
// let id = uN[TEST_ID_W]:0;
// let rw_config = MainCtrlBundle<TEST_ADDR_W> {
// startAddress: u32:0x1000, lineCount: u32:27, lineLength: u32:1, lineStride: u32:0
// start_address: u32:0x1000, line_count: u32:27, line_length: u32:1, line_stride: u32:0
// };
// let init_csr_values = AdrDatPair[u32:10]:[
// (config::READER_START_ADDRESS, rw_config.startAddress),
// (config::READER_LINE_LENGTH, rw_config.lineLength),
// (config::READER_LINE_COUNT, rw_config.lineCount),
// (config::READER_STRIDE_BETWEEN_LINES, rw_config.lineStride),
// (config::WRITER_START_ADDRESS, rw_config.startAddress),
// (config::WRITER_LINE_LENGTH, rw_config.lineLength),
// (config::WRITER_LINE_COUNT, rw_config.lineCount),
// (config::WRITER_STRIDE_BETWEEN_LINES, rw_config.lineStride),
// (config::READER_START_ADDRESS, rw_config.start_address),
// (config::READER_LINE_LENGTH, rw_config.line_length),
// (config::READER_LINE_COUNT, rw_config.line_count),
// (config::READER_STRIDE_BETWEEN_LINES, rw_config.line_stride),
// (config::WRITER_START_ADDRESS, rw_config.start_address),
// (config::WRITER_LINE_LENGTH, rw_config.line_length),
// (config::WRITER_LINE_COUNT, rw_config.line_count),
// (config::WRITER_STRIDE_BETWEEN_LINES, rw_config.line_stride),
// (config::INTERRUPT_MASK_REGISTER, uN[TEST_DATA_W]:3),
// (config::CONTROL_REGISTER, uN[TEST_DATA_W]:63),
// ];
Expand Down Expand Up @@ -609,7 +609,7 @@ proc TestImageInverse {
// let (tok, _) = recv(tok, writer_sync_rsp);

// // Initialize system memory
// let MEM_SIZE = rw_config.lineCount * rw_config.lineLength;
// let MEM_SIZE = rw_config.line_count * rw_config.line_length;
// let system_memory = uN[TEST_DATA_W][MEM_SIZE]:[
// uN[TEST_DATA_W]:0x00, uN[TEST_DATA_W]:0x00, uN[TEST_DATA_W]:0x00,
// uN[TEST_DATA_W]:0x82,
Expand All @@ -627,11 +627,11 @@ proc TestImageInverse {
// ];

// let system_memory_copy = for (_, mem): (u32, uN[TEST_DATA_W][MEM_SIZE]) in
// u32:0..rw_config.lineLength {
// u32:0..rw_config.line_length {
// // Handle AXI Read
// let (tok, axi_ar) = recv(tok, ch_axi_data_ar);
// let addr = (axi_ar.araddr - rw_config.startAddress) >> 2;
// let tok = for (i, tok): (u32, token) in u32:0..rw_config.lineCount {
// let addr = (axi_ar.araddr - rw_config.start_address) >> 2;
// let tok = for (i, tok): (u32, token) in u32:0..rw_config.line_count {
// let tok = send(
// tok, ch_axi_data_r,
// axi_pkg::simpleAxiRBundle<TEST_DATA_W, TEST_ID_W>(
Expand All @@ -642,9 +642,9 @@ proc TestImageInverse {
// // Handle AXI Write
// let (tok, aw) = recv(tok, ch_axi_data_aw);
// let mem = for (i, mem): (u32, uN[TEST_DATA_W][MEM_SIZE]) in
// u32:0..rw_config.lineCount {
// u32:0..rw_config.line_count {
// let (tok, w) = recv(tok, ch_axi_data_w);
// let addr = (aw.awaddr - rw_config.startAddress) >> 2;
// let addr = (aw.awaddr - rw_config.start_address) >> 2;
// let mem = update(mem, addr + i, w.wdata);
// mem
// }(mem);
Expand Down Expand Up @@ -677,6 +677,7 @@ proc TestImageInverse {
// let tok = send(tok, terminator, true);
// }
// }

proc main_controller {
config(ch_axi_ctrl_aw: chan<AxiAwBundle<config::TOP_ADDR_W, config::TOP_ID_W>> in,
ch_axi_ctrl_w: chan<AxiWBundle<config::TOP_DATA_W, config::TOP_STRB_W>> in,
Expand Down

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