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add litex-sys library, fetch constants that svd2rust can't parse from…
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… svf from litex-sys instead
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vk2seb committed Mar 18, 2024
1 parent 249ad67 commit 55bdf04
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Showing 5 changed files with 53 additions and 11 deletions.
3 changes: 3 additions & 0 deletions .gitmodules
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Expand Up @@ -46,3 +46,6 @@
[submodule "deps/pythondata-cpu-vexriscv_smp"]
path = deps/pythondata-cpu-vexriscv_smp
url = https://github.com/litex-hub/pythondata-cpu-vexriscv_smp.git
[submodule "firmware/deps/litex-sys"]
path = firmware/deps/litex-sys
url = [email protected]:schnommus/litex-sys.git
1 change: 1 addition & 0 deletions firmware/deps/litex-sys
Submodule litex-sys added at a76b1a
51 changes: 45 additions & 6 deletions firmware/litex-fw/Cargo.lock

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1 change: 1 addition & 0 deletions firmware/litex-fw/Cargo.toml
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Expand Up @@ -14,6 +14,7 @@ riscv-rt = "*"
panic-halt = "*"
litex-hal = { path = "../deps/rust-litex-hal" }
litex-pac = { path = "../deps/generated-litex-pac", features = ["rt"] }
litex-sys = { path = "../deps/litex-sys" }
micromath = "2.0.0"
heapless = { version = "0.7.16", default-features = false, features = ["ufmt-impl", "atomic-polyfill"] }
ufmt = "0.2.0"
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8 changes: 3 additions & 5 deletions firmware/litex-fw/src/main.rs
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Expand Up @@ -21,6 +21,7 @@ use heapless::*;
use litex_hal::prelude::*;
use litex_hal::uart::UartError;
use litex_pac as pac;
use litex_sys;
use riscv_rt::entry;
use riscv;
use core::arch::asm;
Expand All @@ -33,9 +34,6 @@ use log::*;
use plic::*;
use dsp::*;

/// TODO: Modify `svd2rust` so this can be automatically forwarded?
const SYSTEM_CLOCK_FREQUENCY: u32 = 75_000_000;

/// Number of channels per section (4x input, 4x output)
const N_CHANNELS: usize = 4;

Expand Down Expand Up @@ -66,7 +64,7 @@ static mut KARLSEN_LPF: Option<KarlsenLpf> = None;

// Map the RISCV IRQ PLIC onto the fixed address present in the VexRISCV implementation.
// TODO: ideally fetch this from the svf, its currently not exported by `svd2rust`!
riscv::plic_context!(PLIC0, 0xf0c0_0000, 0, VexInterrupt, VexPriority);
riscv::plic_context!(PLIC0, litex_sys::PLIC_BASE, 0, VexInterrupt, VexPriority);

// Create the HAL bindings for the remaining LiteX peripherals.

Expand Down Expand Up @@ -180,7 +178,7 @@ fn main() -> ! {
log::init(peripherals.UART);
log::info!("hello from litex-fw!");

let mut timer = Timer::new(peripherals.TIMER0, SYSTEM_CLOCK_FREQUENCY);
let mut timer = Timer::new(peripherals.TIMER0, litex_sys::CONFIG_CLOCK_FREQUENCY);

unsafe {
// Create an instance of our DSP function which has some internal state.
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