This is a course from Nation Taiwan University (NTU) in 2024 spring semester by Professor Tzi-Dar Chiueh.
In this course, you will cover the entire IC design flow, including Verilog coding, testbench writing, synthesis, automatic place and route, and post-layout. Each part will include one lab and one homework assignment, along with a team project.
About the team project, your team needs to come up with the proposal on your own, and your work will be sent to TSRI for fabrication.
| Assignment | Part | Description |
|---|---|---|
| Lab1 | Verilog | Learn how to verify your Verilog and how to run the VCS simulator with testbench. |
| Lab2 | Testbench | Debug an ALU. |
| Lab3 | Synthesis | Practice synthesizing a design by using Design Compiler. |
| Lab4 | APR | Practice automatic place & route by using Innovus. |
| Lab5 | Post-layout | Practice design rule check(DRC) and layout versus schematic(LVS) |
| HW1 | Verilog | |
| HW2 | Testbench | |
| HW3 | Synthesis | |
| HW4 | APR | |
| HW5 | Post-layout |
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Architecture
