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clk: fix style and data types
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This commit replaces all platform-dependent data types with fix-sized
types, and unifies the return values of interfaces as signed integers.
The return value 0 indicates the success on the request to clock driver,
and negative values indicate the failure reasons.

Signed-off-by: Terry Bai <[email protected]>
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@terryzbai
terryzbai committed Nov 18, 2024
1 parent 1acc8de commit 0a6c664
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Showing 13 changed files with 479 additions and 802 deletions.
41 changes: 15 additions & 26 deletions drivers/clk/clk-operations.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -122,13 +122,11 @@ const struct clk_ops clk_gate_ro_ops = {
.is_enabled = clk_gate_is_enabled,
};

static inline unsigned long clk_div_recalc_rate(const struct clk *clk,
unsigned long prate)
static inline uint64_t clk_div_recalc_rate(const struct clk *clk, uint64_t prate)
{

struct clk_div_data *data = (struct clk_div_data *)(clk->data);
uint32_t div = regmap_read_bits(clk->base, data->offset, data->shift,
data->width);
uint32_t div = regmap_read_bits(clk->base, data->offset, data->shift, data->width);

/* TODO: Need to verify the following cases */
if (data->flags & CLK_DIVIDER_ONE_BASED) {
Expand All @@ -144,8 +142,7 @@ static inline unsigned long clk_div_recalc_rate(const struct clk *clk,
return DIV_ROUND_UP_ULL((uint64_t)prate, div);
}

static inline int clk_div_set_rate(const struct clk *clk, uint32_t rate,
uint32_t parent_rate)
static inline int clk_div_set_rate(const struct clk *clk, uint64_t rate, uint64_t parent_rate)
{
struct clk_div_data *data = (struct clk_div_data *)(clk->data);
uint32_t div = DIV_ROUND_UP(parent_rate, rate);
Expand All @@ -160,8 +157,7 @@ static inline int clk_div_set_rate(const struct clk *clk, uint32_t rate,
} else {
div -= 1;
}
return regmap_update_bits(clk->base, data->offset, data->shift, data->width,
div);
return regmap_update_bits(clk->base, data->offset, data->shift, data->width, div);
}

const struct clk_ops clk_divider_ops = {
Expand All @@ -180,8 +176,7 @@ static inline uint8_t clk_mux_get_parent(const struct clk *clk)
{
struct clk_mux_data *data = (struct clk_mux_data *)(clk->data);
uint32_t num_parents = clk->hw.init->num_parents;
uint32_t val = regmap_mux_read_bits(clk->base, data->offset, data->shift,
data->mask);
uint32_t val = regmap_mux_read_bits(clk->base, data->offset, data->shift, data->mask);

if (data->table) {
int i;
Expand Down Expand Up @@ -212,12 +207,10 @@ static inline int clk_mux_set_parent(struct clk *clk, uint8_t index)
struct clk_mux_data *data = (struct clk_mux_data *)(clk->data);

if (data->table) {
unsigned int val = data->table[index];
regmap_mux_update_bits(clk->base, data->offset, data->shift, data->mask,
val);
uint32_t val = data->table[index];
regmap_mux_update_bits(clk->base, data->offset, data->shift, data->mask, val);
}
regmap_mux_update_bits(clk->base, data->offset, data->shift, data->mask,
index);
regmap_mux_update_bits(clk->base, data->offset, data->shift, data->mask, index);

return 0;
}
Expand All @@ -231,16 +224,14 @@ const struct clk_ops clk_mux_ro_ops = {
.get_parent = clk_mux_get_parent,
};

static inline unsigned long clk_factor_recalc_rate(const struct clk *clk,
unsigned long parent_rate)
static inline uint64_t clk_factor_recalc_rate(const struct clk *clk, uint64_t parent_rate)
{
struct clk_fixed_factor_data *data =
(struct clk_fixed_factor_data *)(clk->data);
unsigned long long int rate;
struct clk_fixed_factor_data *data = (struct clk_fixed_factor_data *)(clk->data);
uint64_t rate;

rate = (unsigned long long int)parent_rate * data->mult;
rate = (uint64_t)parent_rate * data->mult;
do_div(rate, data->div);
return (unsigned long)rate;
return (uint64_t)rate;
}

const struct clk_ops clk_fixed_factor_ops = {
Expand All @@ -250,17 +241,15 @@ const struct clk_ops clk_fixed_factor_ops = {
/* .recalc_accuracy = clk_factor_recalc_accuracy, */
};

static inline int clk_source_set_rate(const struct clk *clk, uint32_t rate,
uint32_t parent_rate)
static inline int clk_source_set_rate(const struct clk *clk, uint64_t rate, uint64_t parent_rate)
{
struct clk_source_data *data = (struct clk_source_data *)(clk->data);
data->rate = rate;

return 0;
}

static inline unsigned long clk_source_get_rate(const struct clk *clk,
unsigned long prate)
static inline uint64_t clk_source_get_rate(const struct clk *clk, uint64_t prate)
{
struct clk_source_data *data = (struct clk_source_data *)(clk->data);

Expand Down
44 changes: 16 additions & 28 deletions drivers/clk/clk-operations.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -8,11 +8,11 @@
#include <clk.h>
#include <utils.h>

#define CLK_INCORRECT_ARGS 1
#define CLK_INVALID_OP 2
#define CLK_INVALID_ID 3
#define CLK_UNKNOWN_REQ 4
#define CLK_UNKNOWN_TARGET 5
#define CLK_INCORRECT_ARGS -1
#define CLK_INVALID_OP -2
#define CLK_INVALID_ID -3
#define CLK_UNKNOWN_REQ -4
#define CLK_UNKNOWN_TARGET -5

static inline int reg_write(uint64_t base, uint32_t offset, uint32_t val)
{
Expand All @@ -22,8 +22,7 @@ static inline int reg_write(uint64_t base, uint32_t offset, uint32_t val)
return 0;
}

static inline int regmap_update_bits(uint64_t base, uint32_t offset,
uint8_t shift, uint8_t width, uint32_t val)
static inline int regmap_update_bits(uint64_t base, uint32_t offset, uint8_t shift, uint8_t width, uint32_t val)
{
volatile uint32_t *clk_reg = ((void *)base + offset);
uint32_t reg_val = *clk_reg;
Expand All @@ -36,8 +35,7 @@ static inline int regmap_update_bits(uint64_t base, uint32_t offset,
return 0;
}

static inline uint32_t regmap_read_bits(uint64_t base, uint32_t offset,
uint8_t shift, uint8_t width)
static inline uint32_t regmap_read_bits(uint64_t base, uint32_t offset, uint8_t shift, uint8_t width)
{
volatile uint32_t *clk_reg = ((void *)base + offset);
uint32_t reg_val = *clk_reg;
Expand All @@ -48,9 +46,7 @@ static inline uint32_t regmap_read_bits(uint64_t base, uint32_t offset,
return reg_val;
}

static inline int regmap_mux_update_bits(uint64_t base, uint32_t offset,
uint8_t shift, uint32_t mask,
uint32_t val)
static inline int regmap_mux_update_bits(uint64_t base, uint32_t offset, uint8_t shift, uint32_t mask, uint32_t val)
{
volatile uint32_t *clk_reg = ((void *)base + offset);
uint32_t reg_val = *clk_reg;
Expand All @@ -63,8 +59,7 @@ static inline int regmap_mux_update_bits(uint64_t base, uint32_t offset,
return 0;
}

static inline uint32_t regmap_mux_read_bits(uint64_t base, uint32_t offset,
uint8_t shift, uint32_t mask)
static inline uint32_t regmap_mux_read_bits(uint64_t base, uint32_t offset, uint8_t shift, uint32_t mask)
{
volatile uint32_t *clk_reg = ((void *)base + offset);
uint32_t reg_val = *clk_reg;
Expand All @@ -84,8 +79,7 @@ extern const struct clk_ops clk_mux_ro_ops;
extern const struct clk_ops clk_gate_ops;
extern const struct clk_ops clk_gate_ro_ops;

#define CLK_FIXED_FACTOR(_name, _mult, _div, _data_flags, _parent_clks, \
_num_parents, _init_flags) \
#define CLK_FIXED_FACTOR(_name, _mult, _div, _data_flags, _parent_clks, _num_parents, _init_flags) \
struct clk _name = { \
.data = &(struct clk_fixed_factor_data) { \
.mult = (_mult), \
Expand All @@ -101,8 +95,7 @@ struct clk _name = { \
}, \
}

#define CLK_GATE(_name, _offset, _bit, _data_flags, _parent_clks, \
_num_parents, _init_flags) \
#define CLK_GATE(_name, _offset, _bit, _data_flags, _parent_clks, _num_parents, _init_flags) \
struct clk _name = { \
.data = &(struct clk_gate_data) { \
.offset = (_offset), \
Expand All @@ -118,8 +111,7 @@ struct clk _name = { \
}, \
}

#define CLK_GATE_RO(_name, _offset, _bit, _data_flags, _parent_clks, \
_num_parents, _init_flags) \
#define CLK_GATE_RO(_name, _offset, _bit, _data_flags, _parent_clks, _num_parents, _init_flags) \
struct clk _name = { \
.data = &(struct clk_gate_data) { \
.offset = (_offset), \
Expand All @@ -135,8 +127,7 @@ struct clk _name = { \
}, \
}

#define CLK_MUX(_name, _offset, _mask, _shift, _table, _data_flags, \
_parent_data, _num_parents, _init_flags) \
#define CLK_MUX(_name, _offset, _mask, _shift, _table, _data_flags, _parent_data, _num_parents, _init_flags) \
struct clk _name = { \
.data = &(struct clk_mux_data) { \
.offset = (_offset), \
Expand All @@ -154,8 +145,7 @@ struct clk _name = { \
}, \
}

#define CLK_MUX_RO(_name, _offset, _mask, _shift, _table, _data_flags, \
_parent_data, _num_parents, _init_flags) \
#define CLK_MUX_RO(_name, _offset, _mask, _shift, _table, _data_flags, _parent_data, _num_parents, _init_flags) \
struct clk _name = { \
.data = &(struct clk_mux_data) { \
.offset = (_offset), \
Expand All @@ -173,8 +163,7 @@ struct clk _name = { \
}, \
}

#define CLK_DIV(_name, _offset, _shift, _width, _data_flags, _parent_clks, \
_num_parents, _init_flags) \
#define CLK_DIV(_name, _offset, _shift, _width, _data_flags, _parent_clks, _num_parents, _init_flags) \
struct clk _name = { \
.data = &(struct clk_div_data) { \
.offset = (_offset), \
Expand All @@ -191,8 +180,7 @@ struct clk _name = { \
}, \
}

#define CLK_DIV_RO(_name, _offset, _shift, _width, _data_flags, _parent_clks, \
_num_parents, _init_flags) \
#define CLK_DIV_RO(_name, _offset, _shift, _width, _data_flags, _parent_clks, _num_parents, _init_flags) \
struct clk _name = { \
.data = &(struct clk_div_data) { \
.offset = (_offset), \
Expand Down
38 changes: 7 additions & 31 deletions drivers/clk/clk.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -70,8 +70,7 @@ struct clk_init_data;
* clk_foo's clk_ops
*
* @init: pointer to struct clk_init_data that contains the init data shared
* with the common clock framework. This pointer will be set to NULL once
* a clk_register() variant is called on this clk_hw pointer.
* with the common clock framework.
*/
struct clk_hw {
struct clk *clk;
Expand All @@ -83,20 +82,6 @@ struct clk_hw {
* be provided by the clock implementation, and will be called by drivers
* through the clk_* api.
*
* @prepare: Prepare the clock for enabling. This must not return until
* the clock is fully prepared, and it's safe to call clk_enable.
* This callback is intended to allow clock implementations to
* do any initialisation that may sleep. Called with
* prepare_lock held.
*
* @unprepare: Release the clock from its prepared state. This will typically
* undo any work done in the @prepare callback. Called with
* prepare_lock held.
*
* @is_prepared: Queries the hardware to determine if the clock is prepared.
* This function is allowed to sleep. Optional, if this op is not
* set then the prepare count will be used.
*
* @enable: Enable the clock atomically. This must not return until the
* clock is generating a valid clock signal, usable by consumer
* devices. Called with enable_lock held. This function must not
Expand All @@ -109,11 +94,6 @@ struct clk_hw {
* This function must not sleep. Optional, if this op is not
* set then the enable count will be used.
*
* @disable_unused: Disable the clock atomically. Only called from
* clk_disable_unused for gate clocks with special needs.
* Called with enable_lock held. This function must not
* sleep.
*
* @recalc_rate: Recalculate the rate of this clock, by querying hardware. The
* parent rate is an input parameter. It is up to the caller to
* ensure that the prepare_mutex is held across this call. If the
Expand Down Expand Up @@ -165,9 +145,8 @@ struct clk_hw {
struct clk_ops {
uint8_t (*get_parent)(const struct clk *clk);
int (*set_parent)(struct clk *clk, uint8_t index);
unsigned long (*recalc_rate)(const struct clk *clk,
unsigned long parent_rate);
int (*set_rate)(const struct clk *clk, uint32_t rate, uint32_t parent_rate);
uint64_t (*recalc_rate)(const struct clk *clk, uint64_t parent_rate);
int (*set_rate)(const struct clk *clk, uint64_t rate, uint64_t parent_rate);
void (*init)(struct clk *clk);
int (*enable)(struct clk *clk);
int (*disable)(struct clk *clk);
Expand Down Expand Up @@ -334,9 +313,6 @@ struct clk_fixed_factor_data {
* .get_parent clk_op.
* CLK_MUX_ROUND_CLOSEST - Use the parent rate that is closest to the desired
* frequency.
* CLK_MUX_BIG_ENDIAN - By default little endian register accesses are used for
* the mux register. Setting this flag makes the register accesses big
* endian.
*/
struct clk_mux_data {
uint32_t offset;
Expand Down Expand Up @@ -368,21 +344,21 @@ const struct clk *get_parent(const struct clk *clk);
* @clk: pointer to the current clk
*
*/
uint32_t clk_get_rate(const struct clk *clk, uint64_t *rate);
int clk_get_rate(const struct clk *clk, uint64_t *rate);

/**
* function clk_enable() - enable the target clock signal
*
* @clk: pointer to the current clk
*/
uint32_t clk_enable(struct clk *clk);
int clk_enable(struct clk *clk);

/**
* function clk_disable() - disable the target clock signal
*
* @clk: pointer to the current clk
*/
uint32_t clk_disable(struct clk *clk);
int clk_disable(struct clk *clk);

/**
* function clk_set_rate() - set the nearest rate to the requested rate for
Expand All @@ -392,4 +368,4 @@ uint32_t clk_disable(struct clk *clk);
* @req_rate: request rate
* @rate: pointer to result variable
*/
uint32_t clk_set_rate(struct clk *clk, uint64_t req_rate, uint64_t *rate);
int clk_set_rate(struct clk *clk, uint64_t req_rate, uint64_t *rate);
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