clk: fix style and add licenses

This commit fixed style and license issues based on feedback

Signed-off-by: Terry Bai <[email protected]>

drivers/clk/clk-operations.c

@@ -83,22 +83,22 @@
 #include <sddf/timer/client.h>
 #include <sddf/util/printf.h>
 
-static int clk_gate_enable(struct clk *clk)
+static inline int clk_gate_enable(struct clk *clk)
 {
     struct clk_gate_data *data = (struct clk_gate_data *)(clk->data);
 
     return regmap_update_bits(clk->base, data->offset, data->bit_idx, 1, 1);
 }
 
-static int clk_gate_disable(struct clk *clk)
+static inline int clk_gate_disable(struct clk *clk)
 {
     struct clk_gate_data *data = (struct clk_gate_data *)(clk->data);
 
     regmap_update_bits(clk->base, data->offset, data->bit_idx, 1, 0);
     return 0;
 }
 
-static int clk_gate_is_enabled(struct clk *clk)
+static inline int clk_gate_is_enabled(struct clk *clk)
 {
     struct clk_gate_data *data = (struct clk_gate_data *)(clk->data);
 
@@ -122,7 +122,7 @@ const struct clk_ops clk_gate_ro_ops = {
     .is_enabled = clk_gate_is_enabled,
 };
 
-static unsigned long clk_div_recalc_rate(const struct clk *clk,
+static inline unsigned long clk_div_recalc_rate(const struct clk *clk,
                                          unsigned long prate)
 {
 
@@ -144,7 +144,7 @@ static unsigned long clk_div_recalc_rate(const struct clk *clk,
     return DIV_ROUND_UP_ULL((uint64_t)prate, div);
 }
 
-static int clk_div_set_rate(const struct clk *clk, uint32_t rate,
+static inline int clk_div_set_rate(const struct clk *clk, uint32_t rate,
                             uint32_t parent_rate)
 {
     struct clk_div_data *data = (struct clk_div_data *)(clk->data);
@@ -160,8 +160,8 @@ static int clk_div_set_rate(const struct clk *clk, uint32_t rate,
     } else {
         div -= 1;
     }
-    return regmap_update_bits(clk->base, data->offset, data->shift,
-                              data->width, div);
+    return regmap_update_bits(clk->base, data->offset, data->shift, data->width,
+                              div);
 }
 
 const struct clk_ops clk_divider_ops = {
@@ -176,12 +176,12 @@ const struct clk_ops clk_divider_ro_ops = {
     /* .determine_rate = clk_div_determine_rate, */
 };
 
-static uint8_t clk_mux_get_parent(const struct clk *clk)
+static inline uint8_t clk_mux_get_parent(const struct clk *clk)
 {
     struct clk_mux_data *data = (struct clk_mux_data *)(clk->data);
     uint32_t num_parents = clk->hw.init->num_parents;
-    uint32_t val = regmap_mux_read_bits(clk->base, data->offset,
-                                        data->shift, data->mask);
+    uint32_t val = regmap_mux_read_bits(clk->base, data->offset, data->shift,
+                                        data->mask);
 
     if (data->table) {
         int i;
@@ -207,16 +207,17 @@ static uint8_t clk_mux_get_parent(const struct clk *clk)
     return 0;
 }
 
-static int clk_mux_set_parent(struct clk *clk, uint8_t index)
+static inline int clk_mux_set_parent(struct clk *clk, uint8_t index)
 {
     struct clk_mux_data *data = (struct clk_mux_data *)(clk->data);
 
     if (data->table) {
         unsigned int val = data->table[index];
-        regmap_mux_update_bits(clk->base, data->offset, data->shift,
-                               data->mask, val);
+        regmap_mux_update_bits(clk->base, data->offset, data->shift, data->mask,
+                               val);
     }
-    /* TODO: handle cases without table given */
+    regmap_mux_update_bits(clk->base, data->offset, data->shift, data->mask,
+                           index);
 
     return 0;
 }
@@ -230,7 +231,7 @@ const struct clk_ops clk_mux_ro_ops = {
     .get_parent = clk_mux_get_parent,
 };
 
-static unsigned long clk_factor_recalc_rate(const struct clk *clk,
+static inline unsigned long clk_factor_recalc_rate(const struct clk *clk,
                                             unsigned long parent_rate)
 {
     struct clk_fixed_factor_data *data =
@@ -249,7 +250,7 @@ const struct clk_ops clk_fixed_factor_ops = {
     /* .recalc_accuracy = clk_factor_recalc_accuracy, */
 };
 
-static int clk_source_set_rate(const struct clk *clk, uint32_t rate,
+static inline int clk_source_set_rate(const struct clk *clk, uint32_t rate,
                                uint32_t parent_rate)
 {
     struct clk_source_data *data = (struct clk_source_data *)(clk->data);
@@ -258,7 +259,7 @@ static int clk_source_set_rate(const struct clk *clk, uint32_t rate,
     return 0;
 }
 
-static unsigned long clk_source_get_rate(const struct clk *clk,
+static inline unsigned long clk_source_get_rate(const struct clk *clk,
                                          unsigned long prate)
 {
     struct clk_source_data *data = (struct clk_source_data *)(clk->data);

drivers/clk/clk-operations.h

@@ -14,17 +14,17 @@
 #define CLK_UNKNOWN_REQ 4
 #define CLK_UNKNOWN_TARGET 5
 
-static inline uint32_t reg_write(uint64_t base, uint32_t offset, uint32_t val)
+static inline int reg_write(uint64_t base, uint32_t offset, uint32_t val)
 {
     volatile uint32_t *clk_reg = ((void *)base + offset);
     *clk_reg = val;
 
     return 0;
 }
 
-static inline uint32_t regmap_update_bits(uint64_t base, uint32_t offset,
-                                          uint8_t shift, uint8_t width,
-                                          uint32_t val)
+static inline int regmap_update_bits(uint64_t base, uint32_t offset,
+                                     uint8_t shift, uint8_t width,
+                                     uint32_t val)
 {
     volatile uint32_t *clk_reg = ((void *)base + offset);
     uint32_t reg_val = *clk_reg;
@@ -34,8 +34,6 @@ static inline uint32_t regmap_update_bits(uint64_t base, uint32_t offset,
 
     *clk_reg = reg_val;
 
-    /* TODO: Check if the register has been updated correctly */
-
     return 0;
 }
 
@@ -51,9 +49,9 @@ static inline uint32_t regmap_read_bits(uint64_t base, uint32_t offset,
     return reg_val;
 }
 
-static inline uint32_t regmap_mux_update_bits(uint64_t base, uint32_t offset,
-                                              uint8_t shift, uint32_t mask,
-                                              uint32_t val)
+static inline int regmap_mux_update_bits(uint64_t base, uint32_t offset,
+                                         uint8_t shift, uint32_t mask,
+                                         uint32_t val)
 {
     volatile uint32_t *clk_reg = ((void *)base + offset);
     uint32_t reg_val = *clk_reg;
@@ -63,8 +61,6 @@ static inline uint32_t regmap_mux_update_bits(uint64_t base, uint32_t offset,
 
     *clk_reg = reg_val;
 
-    /* TODO: Check if the register has been updated correctly */
-
     return 0;
 }
 
@@ -196,8 +192,8 @@ struct clk _name = {                                                       \
     },                                                                     \
 }
 
-#define CLK_DIV_RO(_name, _offset, _shift, _width, _data_flags,       \
-                   _parent_clks, _num_parents, _init_flags)           \
+#define CLK_DIV_RO(_name, _offset, _shift, _width, _data_flags, _parent_clks, \
+                   _num_parents, _init_flags)                         \
 struct clk _name = {                                                  \
     .data = &(struct clk_div_data) {                                  \
         .offset = (_offset),                                          \

drivers/clk/clk.h

@@ -165,7 +165,8 @@ struct clk_hw {
 struct clk_ops {
     uint8_t (*get_parent)(const struct clk *clk);
     int (*set_parent)(struct clk *clk, uint8_t index);
-    unsigned long (*recalc_rate)(const struct clk *clk, unsigned long parent_rate);
+    unsigned long (*recalc_rate)(const struct clk *clk,
+                                 unsigned long parent_rate);
     int (*set_rate)(const struct clk *clk, uint32_t rate, uint32_t parent_rate);
     void (*init)(struct clk *clk);
     int (*enable)(struct clk *clk);
@@ -237,9 +238,6 @@ struct clk_source_data {
  *    of this register, and mask of gate bits are in higher 16-bit of this
  *    register.  While setting the gate bits, higher 16-bit should also be
  *    updated to indicate changing gate bits.
- * CLK_GATE_BIG_ENDIAN - by default little endian register accesses are used for
- *    the gate register.  Setting this flag makes the register accesses big
- *    endian.
  */
 struct clk_gate_data {
     uint32_t offset;
@@ -282,9 +280,6 @@ struct clk_gate_data {
  * CLK_DIVIDER_MAX_AT_ZERO - For dividers which are like CLK_DIVIDER_ONE_BASED
  *    except when the value read from the register is zero, the divisor is
  *    2^width of the field.
- * CLK_DIVIDER_BIG_ENDIAN - By default little endian register accesses are used
- *    for the divider register.  Setting this flag makes the register accesses
- *    big endian.
  */
 struct clk_div_data {
     uint32_t offset;

drivers/clk/imx/clk-imx.c

@@ -79,17 +79,16 @@ static unsigned long clk_pll_recalc_rate(const struct clk *clk,
     uint64_t rate;
 
     /* Output Divider value is (n + 1) * 2 */
-    uint32_t output_div_val = regmap_read_bits(clk->base, data->offset,
-                                               0, 5);
+    uint32_t output_div_val = regmap_read_bits(clk->base, data->offset, 0, 5);
     output_div_val = (output_div_val + 1) * 2;
 
     /* Valid Frac Divider value is 1 to 2^24 */
-    uint32_t frac_div_val = regmap_read_bits(clk->base, data->offset + 0x4,
-                                             7, 24);
+    uint32_t frac_div_val = regmap_read_bits(clk->base, data->offset + 0x4, 7,
+                                             24);
 
     /* Valid Int Divider value is 1 to 32 */
-    uint32_t int_div_val = regmap_read_bits(clk->base, data->offset + 0x4,
-                                            0, 7);
+    uint32_t int_div_val = regmap_read_bits(clk->base, data->offset + 0x4, 0,
+                                            7);
 
     temp_rate *= prate;
     temp_rate *= frac_div_val;
@@ -203,7 +202,8 @@ static uint8_t imx8m_clk_core_slice_get_parent(const struct clk *clk)
 
 static int imx8m_clk_core_slice_set_parent(struct clk *clk, uint8_t index)
 {
-    struct clk_core_slice_data *data = (struct clk_core_slice_data *)(clk->data);
+    struct clk_core_slice_data *data =
+        (struct clk_core_slice_data *)(clk->data);
 
     /*
      * write twice to make sure non-target interface
@@ -232,16 +232,14 @@ static unsigned long imx8m_clk_common_slice_recalc_rate(const struct clk *clk,
     struct clk_common_slice_data *data =
         (struct clk_common_slice_data *)(clk->data);
 
-    uint32_t prediv_val = regmap_read_bits(clk->base, data->offset,
-                                           data->prevdiv_shift,
-                                           data->prevdiv_width);
+    uint32_t prediv_val = regmap_read_bits(
+        clk->base, data->offset, data->prevdiv_shift, data->prevdiv_width);
     /* Divider value is n+1 */
     unsigned long prediv_rate = DIV_ROUND_UP_ULL((uint64_t)prate,
                                                  prediv_val + 1);
 
-    uint32_t postdiv_val = regmap_read_bits(clk->base, data->offset,
-                                            data->postdiv_shift,
-                                            data->postdiv_width);
+    uint32_t postdiv_val = regmap_read_bits(
+        clk->base, data->offset, data->postdiv_shift, data->postdiv_width);
     /* Divider value is n+1 */
     return DIV_ROUND_UP_ULL((uint64_t)prediv_rate, postdiv_val + 1);
 }
@@ -292,14 +290,14 @@ static unsigned long imx8m_clk_bus_slice_recalc_rate(const struct clk *clk,
 {
     struct clk_bus_slice_data *data = (struct clk_bus_slice_data *)(clk->data);
 
-    uint32_t prediv_val = regmap_read_bits(clk->base, data->offset,
-                                           data->prevdiv_shift, data->prevdiv_width);
+    uint32_t prediv_val = regmap_read_bits(
+        clk->base, data->offset, data->prevdiv_shift, data->prevdiv_width);
     /* Divider value is n+1 */
     unsigned long prediv_rate = DIV_ROUND_UP_ULL((uint64_t)prate,
                                                  prediv_val + 1);
 
-    uint32_t postdiv_val = regmap_read_bits(clk->base, data->offset,
-                                            data->postdiv_shift, data->postdiv_width);
+    uint32_t postdiv_val = regmap_read_bits(
+        clk->base, data->offset, data->postdiv_shift, data->postdiv_width);
     /* Divider value is n+1 */
     return DIV_ROUND_UP_ULL((uint64_t)prediv_rate, postdiv_val + 1);
 }