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PCIe/NVMe Driver #283

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PCIe/NVMe Driver #283

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Commits on Nov 8, 2024

  1. init

    Ivan-Velickovic authored and midnightveil committed Nov 8, 2024
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  2. Basic PCIE bus enumeration

    Signed-off-by: julia <[email protected]>
    midnightveil committed Nov 8, 2024
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  3. Use a pcie_header struct

    Signed-off-by: julia <[email protected]>
    midnightveil committed Nov 8, 2024
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  4. Handle JH7110/PLDA pcie errata

    Signed-off-by: julia <[email protected]>
    midnightveil committed Nov 8, 2024
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  5. type 0 pcie header decoding

    Signed-off-by: julia <[email protected]>
    midnightveil committed Nov 8, 2024
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  6. Remove leftover crud from previous example

    Signed-off-by: julia <[email protected]>
    midnightveil committed Nov 8, 2024
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  7. print 64 bit addresses if we have them

    Signed-off-by: julia <[email protected]>
    midnightveil committed Nov 8, 2024
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  8. pcie print size

    Signed-off-by: julia <[email protected]>
    midnightveil committed Nov 8, 2024
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  9. basic nvme regs read

    Signed-off-by: julia <[email protected]>
    midnightveil committed Nov 8, 2024
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  10. add -Werror for compiling pcie driver

    Signed-off-by: Ivan Velickovic <[email protected]>
    Ivan-Velickovic authored and midnightveil committed Nov 8, 2024
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  11. curr

    Signed-off-by: julia <[email protected]>
    midnightveil committed Nov 8, 2024
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  12. dodgy ready admin controller?

    Signed-off-by: julia <[email protected]>
    midnightveil committed Nov 8, 2024
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  13. Basic working NVMe queue ready

    Signed-off-by: julia <[email protected]>
    midnightveil committed Nov 8, 2024
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  14. add a page size define

    Signed-off-by: julia <[email protected]>
    midnightveil committed Nov 8, 2024
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  15. try to get a actual command

    Signed-off-by: julia <[email protected]>
    midnightveil committed Nov 8, 2024
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  16. actually get admin queue commands working

    Signed-off-by: julia <[email protected]>
    midnightveil committed Nov 8, 2024
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  17. move nvme stuff (mostly) out of the pcie fifle

    Signed-off-by: julia <[email protected]>
    midnightveil committed Nov 8, 2024
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  18. weird broken bug

    Signed-off-by: julia <[email protected]>
    midnightveil committed Nov 8, 2024
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  19. fixed bug :)

    Signed-off-by: julia <[email protected]>
    midnightveil committed Nov 8, 2024
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  20. working nvme queue abstraction?

    Signed-off-by: julia <[email protected]>
    midnightveil committed Nov 8, 2024
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  21. Properly bracketise macro :)

    Signed-off-by: julia <[email protected]>
    midnightveil committed Nov 8, 2024
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  22. create I/O completion queue

    Signed-off-by: julia <[email protected]>
    midnightveil committed Nov 8, 2024
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  23. broken i/o submission queeue

    Signed-off-by: julia <[email protected]>
    midnightveil committed Nov 8, 2024
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  25. figured out the issue... ish... but why??

    Signed-off-by: julia <[email protected]>
    midnightveil committed Nov 8, 2024
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  26. fix MPS; it's a log2-value not just a shifted by 2^12 value

    turns out I was setting the "host page size" config bits incorrectly,
    specifying a required page size alignment of 2^13 (i.e. 0x2000, not
    0x1000).
    
    the first queue was aligned to that, the second was not and was failing.
    at some point i tried using the same queu eaddress for creating both
    queues and that worked; so I went "is this some sort of alignment
    issue?" and went off diving into u-boot to discover it aligns dma
    buffers to 32bytes which didn't help since they were both page aligned
    anyway. anyway so i then just started progressively masking off higher
    and higher bits until the difference between 0x40283000 and 0x40282000
    was that one bit
    
    and then i was like ??? wtf went scouring through nvme docs, only
    alignment i could find was dword aligned... then i realised that was
    mostly talking about PRP entries (scatter-gather list dma) meanwhile i
    was using just contiguous dma because easier, which references CC.MPS...
    which i then looked and i thought just doing PAGE_SIZE >> 12 seemed off
    cause 0x1000 >> 12 = 0x1 and 2^(12 + CC.MPS) is 2^13. and i realised it
    wanted a log2 value not a shifted value
    
    Signed-off-by: julia <[email protected]>
    midnightveil committed Nov 8, 2024
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  27. Move debug code to separate header (for now?)

    Signed-off-by: julia <[email protected]>
    midnightveil committed Nov 8, 2024
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  29. try to read data

    this traps with unimp :(
    
    Signed-off-by: julia <[email protected]>
    midnightveil committed Nov 8, 2024
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  30. i spent way too long trying to figure out why this was trapping...

    .. or being entirely optimised out
    
    https://cerberus.cl.cam.ac.uk/?short/cea8cb
    
    this is undefined behaviour. god I love C
    
    Signed-off-by: julia <[email protected]>
    midnightveil committed Nov 8, 2024
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  31. use PRP entries as this is w hat they are

    Signed-off-by: julia <[email protected]>
    midnightveil committed Nov 8, 2024
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  32. it works!!!

    Signed-off-by: julia <[email protected]>
    midnightveil committed Nov 8, 2024
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  33. fix queue lengths for I/O

    Signed-off-by: julia <[email protected]>
    midnightveil committed Nov 8, 2024
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  34. read & write works

    Signed-off-by: julia <[email protected]>
    midnightveil committed Nov 8, 2024
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  35. Get a PCIe interrupt

    Signed-off-by: julia <[email protected]>
    midnightveil committed Nov 8, 2024
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  36. debug register fix

    Signed-off-by: julia <[email protected]>
    midnightveil committed Nov 8, 2024
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  37. some extra asserts

    Signed-off-by: julia <[email protected]>
    midnightveil committed Nov 8, 2024
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  38. dodgy stuff

    Signed-off-by: julia <[email protected]>
    midnightveil committed Nov 8, 2024
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  39. try to setup qemu

    Signed-off-by: julia <[email protected]>
    midnightveil committed Nov 8, 2024
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  40. qemu reading 0xfffff from nvme

    Signed-off-by: julia <[email protected]>
    midnightveil committed Nov 8, 2024
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  42. nvme regs on qemu have to be above 0x4000_0000

    Signed-off-by: julia <[email protected]>
    midnightveil committed Nov 8, 2024
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  43. remove unaligned reads & writes to doorbells

    these are undefined by PCIe/NVMe specs
    
    Signed-off-by: julia <[email protected]>
    midnightveil committed Nov 8, 2024
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  44. controller caps broken in qemu

    Signed-off-by: julia <[email protected]>
    midnightveil committed Nov 8, 2024
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  45. qemu IRQ!

    Signed-off-by: julia <[email protected]>
    midnightveil committed Nov 8, 2024
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  46. qemu interrupt-y style. I have no idea how this works (it only interr…

    …upt sonce???? even though it should do forever???)
    
    https://www.mail-archive.com/[email protected]/msg931360.html
    
    might be this bug
    
    Signed-off-by: julia <[email protected]>
    midnightveil committed Nov 8, 2024
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  47. ifdef the QEMU-specific behaviour

    Signed-off-by: julia <[email protected]>
    midnightveil committed Nov 8, 2024
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  48. check LE cpu

    Signed-off-by: julia <[email protected]>
    midnightveil committed Nov 8, 2024
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  49. interrupts work in QEMU, at least

    Signed-off-by: julia <[email protected]>
    midnightveil committed Nov 8, 2024
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  50. yes QEMU on riscv is broken in multiple ways

    Signed-off-by: julia <[email protected]>
    midnightveil committed Nov 8, 2024
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  51. Document all the weird behaviours?!??!

    Signed-off-by: julia <[email protected]>
    midnightveil committed Nov 8, 2024
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  52. add TODO

    Signed-off-by: julia <[email protected]>
    midnightveil committed Nov 8, 2024
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  53. fix IRQ comment

    Signed-off-by: julia <[email protected]>
    midnightveil committed Nov 8, 2024
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  54. set microkit sdk env var in zig build

    Signed-off-by: julia <[email protected]>
    midnightveil committed Nov 8, 2024
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  55. mostly-broken rockpro

    Signed-off-by: julia <[email protected]>
    midnightveil committed Nov 8, 2024
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  56. nvme boots ish on rockpro

    Signed-off-by: julia <[email protected]>
    midnightveil committed Nov 8, 2024
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  57. imx8mm pcie evk worky

    Signed-off-by: julia <[email protected]>
    midnightveil committed Nov 8, 2024
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  59. qemu riscv pci size

    midnightveil committed Nov 8, 2024
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Commits on Nov 12, 2024

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