HowTo

An example-based quick tutorial for developers to extend gem5/ThyNVM.

How to add a shared L3 cache?

1. Set cache properties
   Modify configs/common/Caches.py as in commit b77a4e7
2. Add new options
   Modify configs/common/Options.py as in commit 2db5be6
   
3. Change cache config
   Modify configs/common/CacheConfig.py as in commit b62d317
   Tips:
   

• We rely on methods in src/cpu/BaseCPU.py. For example, connectAllPorts() is used to connect cached ports of the CPU to the (shared) cache bus, and all uncached ports directly to the memory bus.
  
• The resulting structure is as below.
  

......
cpu[i].toL2Bus
     |(master)
     |(cpu_side)
cpu[i].l2cache
     |(mem_side/cpu[i]._cached_ports)
     |(slave)
system.tol3bus
     |(master)
     |(cpu_side)
system.l3
     |(mem_side)       cpu[i]._uncached_slave/master_ports
     |(slave)                       |(master/slave) 
system.membus----------------------|

How to have both DRAM and NVM in parallel?

1. Add a new class for NVM
   For a typical setup, refer to commit a3a4a69. If a new file is created, we have to include it in the SConscript of the same directory.
2. Add a virtual crossbar class for logic connection purpose only
   VirtualXBar is added in commit 9d3cb9f.
3. Create and connect both memory controllers
   We need new options and a function to do so as in commit 4e64916.
4. Compose the simulation script for ThyNVM system-call emulation (SE)
   The differences between this script and the example SE script configs/example/se.py can be found in commit 0662602.