Big commit, see full commit message for details.

Okay, so a lot of things happened with this one. Let's start with the changes to
the demo driver function.

- I've reordered the function definitions in the big `let` to better reflect the
  order they're initially used in.
- I've added in a function to deassert `probe_all_programmed`. Currently this is
  not necessary, however, if in the future more test cases are added to be run
  on this DUT, `probe_all_programmed` must be deasserted between each of them.
  However since the post function was removed from the HITL infra, the only way
  to do this currently is to make sure that the probe is deasserted before
  anything else happens in the driver function.
- Unnecessary dumps of stdout/stderr of various handles were removed. These
  were only there from earlier debugging attempts and are no longer necessary.
- Timeouts on cleanup for GDB and OpenOCD were extended from 5s to 10s.
- GDB stdout is set to line buffering on our side. Hopefully GDB also does this.
- Added in a whoami check to ensure that each of the CPUs reports its identity
  and that that report is what it should be.
- THE TEST START PROBE IS ACTUALLY ASSERTED NOW, HOW ON EARTH DID I FORGET TO
  DO THIS PREVIOUSLY
- `probe_all_programmed` is asserted.

In `bittide/src/Bittide/Wishbone.hs`:

- Added `wbAlwaysAckWith` and `whoAmIC`. The second one uses the first in order
  to report back a 4 byte identifier whenever accessed over the Wishbone bus.

In `bittide-instances/src/Bittide/Instances/Hitl/Demo.hs`:

- Each component was given a unique address in the management unit processing
  element config, and a `whoAmIC` component was added.
- `whoAmIC` component added to SwCc at the same address as in the management
  unit.
- A debug ILA was added to both the DUT and test top entity.
- Naming and definitions of the FIFO overflow/underflow signals were changed.
  Previously they would only ever assert `True` if ALL FIFOs overflowed or
  underflowed, now they will assert if ANY do. Furthermore, in the test top
  entity they were used as `noFifoOverflows`/`noFifoUnderflows` without actually
  inverting the signals, so that was fixed.

In `firmware-binaries/management-unit/memory.x`:

- The address of data memory was changed to reflect the updated PE config.

In `bittide-instances/data/openocd/vexriscv-2chain.tcl`:

                                                                               |
- Added back in the environment variable grabbing for the TCL and telnet ports.
- Updated target definitions so that they use ports in the opposite order as
  JTAG taps. Why do the taps and ports go in the opposite order that I expected?
  Excellent question, and I don't even have the beginnings of an answer to it.

bittide-instances/data/openocd/vexriscv-2chain.tcl

@@ -11,6 +11,26 @@ if { $user_gdb_port_b == "" } {
   error "Required environment variable 'DEV_B_GDB' not set."
 }
 
+set user_tcl_port_a [env DEV_A_TCL]
+if { $user_tcl_port_a == "" } {
+  error "Required environment variable 'DEV_A_TCL' not set."
+}
+
+set user_tcl_port_b [env DEV_B_TCL]
+if { $user_tcl_port_b == "" } {
+  error "Required environment variable 'DEV_B_TCL' not set."
+}
+
+set user_tel_port_a [env DEV_A_TEL]
+if { $user_tel_port_a == "" } {
+  error "Required environment variable 'DEV_A_TEL' not set."
+}
+
+set user_tel_port_b [env DEV_B_TEL]
+if { $user_tel_port_b == "" } {
+  error "Required environment variable 'DEV_B_TEL' not set."
+}
+
 set git_top_level [string trim [exec git rev-parse --show-toplevel]]
 
 set _ENDIAN little
@@ -29,11 +49,15 @@ set _CHIPNAME vexrisc_ocd
 jtag newtap $_CHIPNAME chain0 -expected-id $_CPUTAPID -irlen 4 -ircapture 0x1 -irmask 0x0F
 jtag newtap $_CHIPNAME chain1 -expected-id $_CPUTAPID -irlen 4 -ircapture 0x1 -irmask 0x03
 
-target create $_CHIPNAME.cpu1 vexriscv -endian $_ENDIAN -chain-position $_CHIPNAME.bridge1 -gdb-port $user_gdb_port_b
+target create $_CHIPNAME.cpu1 vexriscv -endian $_ENDIAN -chain-position $_CHIPNAME.chain1 -gdb-port $user_gdb_port_a
+tcl_port $user_tcl_port_a
+telnet_port $user_tel_port_a
 vexriscv readWaitCycles 10
 vexriscv cpuConfigFile [file join $git_top_level clash-vexriscv clash-vexriscv example-cpu ExampleCpu.yaml]
 
-target create $_CHIPNAME.cpu0 vexriscv -endian $_ENDIAN -chain-position $_CHIPNAME.bridge0 -gdb-port $user_gdb_port_a
+target create $_CHIPNAME.cpu0 vexriscv -endian $_ENDIAN -chain-position $_CHIPNAME.chain0 -gdb-port $user_gdb_port_b
+tcl_port $user_tcl_port_b
+telnet_port $user_tel_port_b
 vexriscv readWaitCycles 10
 vexriscv cpuConfigFile [file join $git_top_level clash-vexriscv clash-vexriscv example-cpu ExampleCpu.yaml]